Hardware Randomizer Using XOR and ALU Pipelines
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Solution Overview
Problem
Software approaches for randomizing data are too slow, posing a challenge in various computing and communication applications.
Innovation Solution
A fast pipelined architecture randomizer is implemented using exclusive-ors (XOR) and an arithmetic logic unit (ALU), capable of expanding input width in 72 bit increments with minimal delay, producing uniformly distributed output across all bits, even when inputs are similar, and handling data at high frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If software approaches are used for randomizing data, then implementation flexibility is maintained, but processing speed becomes too slow
Solution Approach 1:
The patent replaces software-based randomization (mechanical/computational system) with a dedicated hardware circuit system. The randomizer apparatus uses physical hardware components including XOR gates, ALU units, and multiplexers to perform randomization operations in parallel, achieving significant speed improvement over sequential software processing while managing hardware complexity through modular design.
Solution Approach 2:
The randomizer is divided into multiple pipeline stages, each handling specific operations (XOR operations, ALU computations, multiplexing). This segmentation allows each stage to be optimized independently and enables parallel processing across stages, increasing overall throughput while keeping individual stage complexity manageable.
2Productivity
If input width is expanded to handle wider data, then processing capability increases, but delay increases
Solution Approach 1:
The patent implements a pipelined architecture where the randomizer processes multiple 72-bit input words simultaneously at different stages of the pipeline. While each individual path maintains minimal delay, the overall system achieves higher productivity by processing multiple inputs in parallel through dynamically staged operations.
Solution Approach 2:
Instead of increasing the width of a single processing path (which would increase delay), the patent adds another dimension by implementing multiple pipeline stages that process multiple input words concurrently. This transforms the problem from a single-wide high-delay path to a multi-wide parallel pipeline with minimal per-stage delay.
3Speed
If high-frequency operation is achieved, then processing speed increases, but maintaining uniform output distribution becomes more difficult
Solution Approach 1:
The pipelined architecture ensures continuous processing at high frequency by keeping all pipeline stages actively working simultaneously. Each stage performs its function continuously without waiting for other stages, maintaining steady-state high-frequency operation while the deterministic logic operations (XOR, ALU) ensure uniform output distribution is preserved regardless of operating speed.
Data Source
AI summary
The randomizer includes connection circuitry with a random connection layout to parallely couple each of a quantity of bits for each of a plurality of inputs of bit width n to multiple output bits of a respectively coupled output. Combinational circuitry combines at least a portion of each of the plurality of outputs associated with each of the plurality of inputs to create a single resultant output of random data having a bit width of the quantity n.