Cache Architecture Using XOR Encoding for Power Reduction

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Solution Overview

Problem

Existing cache architectures for computer systems, particularly in mobile devices, consume significant power due to their design, with existing technologies providing only incremental improvements, necessitating a more efficient approach to minimize power consumption.

Innovation Solution

A cache architecture that employs an XOR function to process data, reducing the number of bits stored by encoding and indexing zeros, thereby minimizing power consumption, with the XOR operation being performed in parallel to other cache access operations, and utilizing a dual-part cache structure to differentiate between frequently and less frequently changed data bits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If conventional cache memory designs are used, then cache capacity and data storage are sufficient, but power consumption is high (up to 80% of on-chip transistors)

Engineering Contradiction:

Improvepower consumptionVSAvoidnumber of transistors

Core Design Contradiction:

Use of energy by moving objectVSQuantity of substance

Solution Approach 1:

The cache memory is divided into two separate data paths: a low-order bit data path that processes and stores less significant bits, and a high-order bit data path that processes and stores more significant bits. This segmentation allows the cache to store only the necessary bits for each data element, reducing the total number of transistors required while maintaining adequate cache capacity for power-efficient operation

Inventive Principle:

Principle #1Segmentation

2Use of energy by moving object

If cache size is reduced to lower power consumption, then power usage decreases, but cache miss rate increases causing performance penalty

Engineering Contradiction:

Improvepower consumptionVSAvoidperformance

Core Design Contradiction:

Use of energy by moving objectVSProductivity

Solution Approach 1:

The invention introduces a new dimensional approach by separating cache storage into two distinct data paths based on bit significance rather than treating all bits uniformly. This dimensional change allows the cache to maintain effective capacity for performance while physically reducing the total transistor count for power consumption, breaking the traditional trade-off between cache size and power usage

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS7966452B2Cache architecture for a processing unit providing reduced power consumption in cache operation

Publication Date: 2011.06.21 BOARD OF GOVERNORS FOR HIGHER EDUCATION STATE OF RHODE ISLAND & PROVIDENCE PLANTATIONS

AI summary

A cache memory processing system is disclosed that is coupled to a main memory and a processing unit. The cache memory processing system includes an input, a low order bit data path, a high order bit data path and an output. The input is for receiving input data that includes at least one low order input bit and at least one high order input bit. The low order bit data path is for processing the at least one low order input bit and providing at least one low order output bit. The high order bit data path for processing the at least one high order input bit and providing at least one high order output bit. The high order bit data path includes at least one exclusive or gate. The output is for providing the at least one low order output bit and the at least one high order output bit.