XOR Logic Circuit Topology for Low-Delay DDR4 CRC Generation
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Solution Overview
Problem
Existing XOR gate circuits in DDR4 DRAM systems are inefficient due to a large number of elements, increased circuitry area, higher transistor count leading to signal delay, and lack of driver capability resulting in dull waveforms.
Innovation Solution
A logic circuit utilizing 12 transistors to function as both XOR and XNOR gate circuits, with output signals passing through only two transistors in any logic state, providing a driver capability to reduce signal delay and waveform dullness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional XOR gate circuits are used to generate CRC codes, then the XOR operation can be performed, but the circuitry area increases due to a large number of elements
Solution Approach 1:
The patent combines XOR and XNOR gate functions into a single unified circuit structure using 12 transistors. The circuit generates both XOR output (Y) and XNOR output (Yn) simultaneously from the same input signals (A, An, B, Bn), eliminating the need for separate XOR and XNOR circuit implementations and reducing overall circuitry area.
Solution Approach 2:
The invented circuit structure serves multiple functions: it performs XOR operation, XNOR operation, and provides driver capability for output signals. The same 12-transistor circuit generates both Y and Yn outputs with proper drive strength, making the circuit universal and eliminating the need for additional dedicated circuits for each function.
2Reliability
If conventional XOR gate circuits with many transistors are used, then the XOR operation can be implemented, but signal delay increases due to a larger number of transistors that signals must pass through
Solution Approach 1:
The circuit is segmented into parallel signal paths with controlled transistor counts. Each output signal (Y and Yn) passes through a limited number of transistor channels (two transistors in series for each output), preventing excessive signal delay. The 12 transistors are organized into multiple parallel paths rather than a single long chain, reducing the critical path delay.
3Reliability
If conventional XOR gate circuits are used, then the XOR operation can be performed, but waveform quality deteriorates due to lack of driver capability
Solution Approach 1:
The circuit provides self-driven output capability through its inherent transistor configuration. The output nodes (Y and Yn) are directly driven by the transistor switches within the circuit itself, eliminating the need for external buffer or driver circuits. The circuit serves its own driving function, maintaining strong signal levels and clean waveforms without additional components.
Data Source
AI summary
Disclosed herein is a logic circuit that includes a transistor T1 coupled between VPERI and a node n1, a transistor T2 coupled between VPERI and a node n2, a transistor T3 coupled between VSS and a node n3, a transistor T4 coupled between VSS and a node n4, transistors T5 and T7 coupled in series between the nodes n1 and n3, transistors T9 and T11 coupled in series between the nodes n1 and n3, transistors T6 and T8 coupled in series between the nodes n2 and n4, and transistors T10 and T12 coupled in series between the nodes n2 and n4. An output signal Y is output from a connection point of the transistors T5 and T7 and a connection point of the transistors T6 and T8.