XOR Logic Circuit With Full-Swing Output at Low Input Voltage
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Solution Overview
Problem
Conventional XOR logic circuits in semiconductor memory devices face issues with data loss and instability due to threshold voltage drops, especially when handling low voltage input signals, and require a large number of transistors, leading to increased chip area and potential malfunctions.
Innovation Solution
The XOR logic circuit design incorporates a first transfer unit for logic high data, a multiplexing unit for voltage output, and a second transfer unit for logic low data, minimizing transistor count and preventing threshold voltage loss, while maintaining a full swing output signal between power and ground voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional XOR logic circuit uses multiple transistors to handle logic operations, then the circuit can perform buffering operations, but the chip area increases and threshold voltage drops occur causing data loss
Solution Approach 1:
The XOR logic circuit is segmented into distinct functional units: a first transfer unit for transferring logic high level data, a second transfer unit for transferring logic low level data, and a multiplexing unit for selecting between power voltage and ground voltage. This segmentation allows each unit to perform its specific function efficiently without requiring excessive transistors, thereby reducing chip area while maintaining data stability.
Solution Approach 2:
The multiplexing unit acts as an intermediary between the transfer units and the output, selecting either power voltage or ground voltage based on the input conditions. This intermediary component enables the circuit to maintain full swing output signals without requiring additional buffering transistors, thus preventing threshold voltage drops while minimizing chip area.
2Productivity
If the XOR logic circuit transfers logic high level data through multiple transistor stages, then the data can be processed, but threshold voltage drops occur causing data loss
Solution Approach 1:
The data transfer function is segmented into dedicated transfer units: the first transfer unit handles logic high level data transfer using PMOS transistors, while the second transfer unit handles logic low level data transfer using NMOS transistors. This segmentation ensures that each transfer path is optimized for its specific data type, preventing threshold voltage drops and data loss while maintaining efficient data transfer capability.
Solution Approach 2:
The circuit changes the voltage parameter dynamically by using the multiplexing unit to select between power voltage (VDD) and ground voltage (VSS) based on input conditions. This parameter change ensures that the output signal maintains full swing characteristics, preventing threshold voltage drops that would otherwise cause data loss during transfer.
3Reliability
If the XOR logic circuit uses a larger number of transistors for stable operation, then buffering can be performed, but the device complexity increases
Solution Approach 1:
The circuit is segmented into three functional units with clearly defined roles: first transfer unit, second transfer unit, and multiplexing unit. This segmentation provides operational stability through dedicated functions while keeping the overall transistor count low, as each segment performs its specific task without redundancy.
Solution Approach 2:
The multiplexing unit serves multiple functions: it selects between power voltage and ground voltage, controls the output signal level, and works in conjunction with both transfer units. This multi-functionality reduces the need for separate buffering transistors, thereby reducing device complexity while maintaining operation stability.
Data Source
AI summary
An XOR logic circuit includes a first transfer unit configured to transfer a logic high level data to an output terminal in response to data applied to first and second input terminals; a multiplexing unit configured to output a power voltage or a ground voltage in response to the data applied to the first and second input terminals; and a second transfer unit configured to transfer a logic low level data to the output terminal in response to an output signal of the multiplexing unit and the data applied to the first and second input terminals.