Bi-directional XOR Circuit for Latency-Free Processor Memory Encryption
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Solution Overview
Problem
Current computer systems face challenges in securing data transmission between a processor and memory due to slow CPU throughput and latency issues when using encryption/decryption software, which can be compromised by other CPU processes, especially when dealing with high-speed memory types like DDR4 SDRAM.
Innovation Solution
A bi-directional XOR circuit is introduced, emulating both processor and memory protocols, allowing for encryption and decryption operations without adding latency by executing XOR operations within the same clock time as data transmission, thus maintaining the speed of DDR4 interfaces without reducing clock speed or adding extra clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If encryption/decryption software is used to secure data transmission between processor and memory, then security is improved, but CPU throughput decreases and latency increases
Solution Approach 1:
The encryption/decryption function is extracted from the CPU software environment and implemented as a separate hardware circuit. This removes the security processing burden from the CPU, allowing the CPU to maintain full throughput while the dedicated hardware circuit provides security operations without interference from other CPU processes.
Solution Approach 2:
A hardware XOR circuit is introduced as an intermediary component between the processor and memory. This circuit performs encryption/decryption operations on data in transit without requiring CPU intervention, thus maintaining CPU throughput while providing security. The intermediary hardware circuit handles security operations independently, preventing other CPU processes from affecting security performance.
2Reliability
If encryption/decryption software is used to secure data transmission, then security is improved, but latency is added to data operations
Solution Approach 1:
The encryption/decryption function is extracted from the CPU software environment and implemented as a separate hardware circuit. This removes the security processing burden from the CPU, allowing the CPU to maintain full throughput while the dedicated hardware circuit provides security operations without interference from other CPU processes.
Solution Approach 2:
The software-based encryption/decryption process is replaced with a hardware-based XOR circuit that performs operations in parallel with data transmission. This substitution eliminates the sequential processing delays inherent in software execution, achieving security operations at wire-speed without adding latency to data operations.
3Speed
If encryption operations are performed at DDR4 memory speed, then data transmission speed is maintained, but complex hardware circuitry is required
Solution Approach 1:
The encryption approach uses simple XOR operations with dynamically generated keystreams rather than complex encryption algorithms. By changing the operational parameters to use straightforward bitwise operations that can be executed in parallel, the circuit achieves DDR4 memory speed encryption without requiring complex hardware circuitry. The keystream generation and XOR operations are designed to match the timing requirements of DDR4 interfaces.
Data Source
AI summary
An embodiment is directed to a hardware circuit for performing operations on data transmitted between a processor and memory. The hardware circuit includes a first interface communicatively coupled to the processor. The first interface configured to emulate a first protocol of the memory. The hardware circuit further includes a second interface communicatively coupled to the memory. The second interface configured to emulates a second protocol of the processor. The hardware circuit also includes hardware logic configured with a bi-directional path, such that each of the first and second interfaces is associated with a different direction of the bi-directional path. The bi-directional path is configured to execute an operation on data received at both the first interface and the second interface.