Sequential Clock Gating Using XOR Stability Analysis
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Solution Overview
Problem
Current methods for sequential clock gating in system on chip (SOC) integrated circuits are inadequate, as they fail to identify stability conditions for all cases, neglect net activity, and cannot effectively cover synthesis in gated pipeline designs, leading to inefficient power reduction and limited clock gating probability.
Innovation Solution
A computation and design synthesis method using XOR-based techniques to compute stability conditions for flip-flops, combining delayed and inverted signals to generate consolidated clock gating signals, effectively addressing the limitations of prior art by considering primary inputs, enabled, and unenabled flops within the fan-in path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If sequential clock gating is implemented using traditional STC computation methods, then power reduction is achieved, but the methods fail to identify stability conditions for all cases and cannot cover synthesis in gated pipeline designs
Solution Approach 1:
The patent inverts the traditional approach by using XOR gates to detect changes in stability conditions rather than using traditional combinational analysis. The XOR gate outputs high when inputs differ, enabling detection of stability condition changes in sequential circuits including gated pipeline designs, thereby expanding coverage while maintaining power reduction effectiveness
Solution Approach 2:
The patent introduces dynamic analysis to compute stability conditions sequentially through time frames, allowing the method to adapt to gated pipeline designs where traditional static analysis fails. The dynamic computation traverses fan-in paths through multiple clock cycles, enabling coverage of previously unreachable cases while achieving comprehensive clock gating synthesis
2Ease of manufacture
If traditional STC computation methods are used, then synthesis can be performed, but net activity is not taken into account leading to limited clock gating probability
Solution Approach 1:
The patent incorporates feedback mechanisms by computing stability conditions through sequential analysis that considers net activity. The method uses feedback loops to traverse fan-in paths and detect when stability conditions change, allowing the synthesis tool to identify more clock gating opportunities by accounting for actual signal activity rather than assuming worst-case scenarios
Solution Approach 2:
The patent performs preliminary computation of stability conditions using XOR gates before final clock gating synthesis. By pre-computing stability conditions and detecting changes in advance, the method identifies additional clock gating opportunities that traditional methods miss, increasing clock gating probability while maintaining synthesis capability
Data Source
AI summary
The circuit design process requires ways to reduce the power consumption of large integrated circuits and system-on-chip designs. This is typically done by introducing a process of clock gating thereby enabling or disabling flip-flops associated with specific functional blocks within the circuit. However, such changes in the circuit require synthesis and verification to ensure correctness of design and operation as sequential clock gating changes the state function dynamically. It is therefore necessary to define synthesis methods adapted to such dynamic changes in the design. According to an embodiment a sequential clock gating method uses an exclusive-OR technique to overcome the deficiencies of the prior art methods.