Cross-Coupled XOR Clock Generator for Non-Overlap Timing
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Solution Overview
Problem
Conventional non-overlapping clock generators require excessive circuit area and current consumption, especially when dealing with lower frequencies or longer non-overlapping periods.
Innovation Solution
A non-overlapping clock generator design utilizing cross-coupled XOR gates with load transistors and delay circuits to generate in-phase and reversed-phase output clock signals, where the non-overlapping period is controlled by a control voltage and delay periods, reducing circuit area and current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional non-overlapping clock generator uses NAND gates and cascaded NOT gates, then it can generate non-overlapping clock signals, but it requires excessively large circuit area and consumes larger current when input clock frequency is lower or non-overlapping period is longer
Solution Approach 1:
The patent changes the logic gate type from NAND gates to XOR gates, which fundamentally alters the circuit's operational characteristics. XOR gates naturally produce non-overlapping outputs when cross-coupled, eliminating the need for additional NOT gates and cascaded stages. This parameter change in gate type directly reduces circuit area while maintaining the non-overlapping clock signal generation function.
Solution Approach 2:
The patent extracts and removes the unnecessary cascaded NOT gates from the conventional design. By using cross-coupled XOR gates alone, the circuit achieves non-overlapping output directly without requiring the extra inverting stages, thereby reducing circuit area and simplifying the overall structure.
2Reliability
If conventional non-overlapping clock generator uses NAND gates and cascaded NOT gates, then it can generate non-overlapping clock signals, but it consumes excessively large current when input clock frequency is lower or non-overlapping period is longer
Solution Approach 1:
Changing from NAND gates to XOR gates alters the switching characteristics and power consumption profile of the circuit. XOR gates in cross-coupled configuration have lower static power consumption and more efficient dynamic switching, particularly at lower frequencies, thereby reducing overall current consumption while maintaining reliable non-overlapping signal generation.
Solution Approach 2:
The patent utilizes the inherent periodic switching behavior of cross-coupled XOR gates to generate non-overlapping clocks. The circuit naturally alternates between states in a periodic manner determined by the input clock and internal feedback, eliminating the need for continuous activation of multiple gate stages and reducing average current consumption.
3Reliability
If conventional non-overlapping clock generator uses NAND gates and cascaded NOT gates, then it can generate non-overlapping clock signals, but it requires excessively large circuit area when non-overlapping period is longer
Solution Approach 1:
The patent changes the gate configuration to cross-coupled XOR gates, which inherently support adjustable non-overlapping periods through control voltage inputs. This parameter change allows the circuit to generate longer non-overlapping periods without requiring additional cascaded stages, as the XOR gate configuration naturally accommodates variable timing requirements through its logic operation characteristics.
Data Source
AI summary
A non-overlapping clock generator generating an in-phase output clock signal and a reversed-phase output clock signal which are non-overlapped with each other, includes: a first and a second XOR gates, a first and a second load transistors, which are cross coupled, and includes: a first and a second delay circuits. The first delay circuit is coupled between the in-phase output clock signal and a control terminal of the first load transistor. The second delay circuit is coupled between the reversed-phase output clock signal and a control terminal of the second load transistor. Each of the XOR gates includes at least one pass transistor logic circuit configured to execute XOR logic operation and coupled to a first control voltage. A non-overlapping period is determined according to the first control voltage and/or a first delay period of the first delay circuit and a second delay period of the second delay circuit.