Superconducting XOR Gate Timing With Delayed Decision Pulses
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Solution Overview
Problem
Superconducting XOR gates with more than two inputs operate out-of-phase, leading to increased latency in logic operations, which is inefficient in arithmetic units like multipliers.
Innovation Solution
A superconducting XOR-gate system that includes a pulse generator to produce a decision pulse, with input and output XOR gates performing XOR functions on the same phase of a clock signal, using delayed pulses to synchronize operations and mitigate timing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If XOR gates are implemented on different phase boundaries of clock signals in wave-pipeline superconducting technologies, then each XOR gate can operate independently, but XOR gates with more than two inputs operate out-of-phase leading to increased latency
Solution Approach 1:
The patent combines multiple XOR gate operations into a single clock phase by using a tree-structured arrangement where intermediate XOR gates and final output XOR gate all operate synchronously on the same clock phase, eliminating the out-of-phase operation problem and reducing latency
Solution Approach 2:
The patent uses preliminary routing of clock signals and decision pulses to ensure all XOR gates are properly biased and ready to operate simultaneously on the same clock phase, with intermediate XOR gates receiving clock signals in advance to maintain synchronization
Data Source
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AI summary
A superconducting XOR-gate system (100) including a pulse generator (104) configured to generate a decision pulse (PLS). The system also includes an input superconducting XOR-2 gate (102) that receives a first superconducting logic input signal (IN1) and a second superconducting logic input signal and is configured to perform a logic XOR function based on the decision pulse (PLS) on a given phase of a clock signal to provide an intermediate superconducting logic output signal (IOx). The system (100) also includes an output superconducting XOR-2 gate (106) that receives the intermediate superconducting logic output signal and a third superconducting logic input signal and is configured to perform a logic XOR function based on the decision pulse on the given phase of the clock signal to provide a superconducting logic output signal (OUTx).