XOR ECC Circuit for Byte Parity and SECDED Conversion
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Solution Overview
Problem
Existing error detecting/correcting code technologies face challenges in efficiently generating and utilizing redundant portions between different codes, such as byte parity codes and SECDED codes, leading to increased circuit complexity and latency.
Innovation Solution
The implementation of an error detecting/correcting code generating circuit using Exclusive-OR operations to generate redundant portions, allowing for mutual utilization and conversion between byte parity codes and SECDED codes, reducing the number of circuits and execution latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate circuits are used for generating byte parity codes and SECDED codes, then error detection and correction capabilities are provided, but circuit complexity increases
Solution Approach 1:
The patent merges the byte parity code generation circuit and the SECDED code generation circuit into a single integrated circuit. The circuit uses a shared XOR operation unit that can be configured to generate either byte parity codes or SECDED codes based on control signals, eliminating the need for separate independent circuits for each error detection/correction method.
Solution Approach 2:
The generated code unit is designed to perform multiple functions: it can generate byte parity codes for simple error detection, generate SECDED codes for single-bit error correction and double-bit error detection, and convert between different code formats. This multi-functional design reduces overall system complexity while maintaining comprehensive error handling capabilities.
2Reliability
If multiple independent circuits are implemented for code generation and conversion, then comprehensive error handling is achieved, but execution latency increases
Solution Approach 1:
The patent combines code generation and code conversion functions into a single circuit unit, allowing simultaneous execution of multiple operations. The shared XOR operation unit can process data through different operational modes (byte parity generation, SECDED generation, code conversion) without requiring sequential processing through separate circuits, thereby reducing execution latency.
Solution Approach 2:
The circuit performs preliminary preparation by maintaining the generated code and conversion capabilities in a ready state within the same circuit unit. When data requires error detection or correction, the circuit can immediately switch to the appropriate operational mode without the setup time required for inter-circuit data transfer or initialization.
3Adaptability or versatility
If separate generation methods are used for different error detection codes, then code specificity is maintained, but the number of circuits increases
Solution Approach 1:
The circuit is designed with universal functionality to generate multiple types of error detection codes (byte parity codes and SECDED codes) and perform conversions between them. By using a single configurable circuit with control signals that determine the operational mode, the patent maintains adaptability to different code requirements while significantly reducing the total number of circuits needed.
Data Source
AI summary
An error detecting/correcting code generating circuit includes a first exclusive OR operation circuit that generates log2(n+1) bits of one portion of a redundant portion of error detecting/correcting-code-attached data by rounding up the numbers to the right of the decimal point of log2(n+1) in response to the input of m bytes of an information portion included in error-detection-bit-attached data. The error-detection-bit-attached data includes a redundant portion of m bits of error detection bits allocated to the m bytes of the information portion, the byte having n bits. The circuit also includes a second exclusive OR operation circuit that generates m bits of another portion of the redundant portion of the error detecting/correcting-code-attached data in response to the input of the one portion and the error detection bits.