Symmetric XOR Frequency Doubler for Low Deterministic Jitter
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Solution Overview
Problem
Frequency doublers in phase locked loops face challenges with deterministic jitter due to variations in semiconductor processes, affecting the uniformity of time delays and propagation delays between delay units and XOR gates.
Innovation Solution
A frequency doubler design incorporating a voltage-controlled oscillator with N nodes and an XOR gate, where the voltage-controlled oscillator includes inverter units that ensure equal time delays between phases, and the XOR gate has a symmetric configuration to minimize transistor mismatches and R/C time constant mismatches, resulting in reduced deterministic jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional frequency doubler design is used, then frequency doubling function is achieved, but deterministic jitter increases due to process variations
Solution Approach 1:
The patent applies asymmetry principle by intentionally designing the XOR gate with symmetric configuration where each input signal path contains the same number of inverter units (two inverters each). This symmetric design compensates for process variations by ensuring that all signal paths experience identical delays, thereby reducing deterministic jitter. The symmetry ensures that even when transistor parameters vary due to manufacturing processes, the differential delays remain balanced.
Solution Approach 2:
The patent changes the structural parameter of the XOR gate by configuring it with multiple inverter units in each signal path rather than using a conventional single inverter or asymmetric structure. By adjusting the number of inverter units to be equal in each path (two inverters per path), the design modifies the time delay parameters to be uniform across all inputs, which directly addresses the deterministic jitter issue caused by process variations.
2Device complexity
If asymmetric XOR gate configuration is used, then circuit complexity is reduced, but transistor mismatches and R/C time constant mismatches increase
Solution Approach 1:
The patent applies asymmetry principle by intentionally designing the XOR gate with symmetric configuration where each input signal path contains the same number of inverter units (two inverter units per path). This symmetric design compensates for process variations by ensuring that all signal paths experience identical delays, thereby reducing deterministic jitter. The symmetry ensures that even when transistor parameters vary due to manufacturing processes, the differential delays remain balanced.
3Ease of manufacture
If VCO nodes are not uniformly arranged, then layout flexibility is improved, but time delay uniformity between phases deteriorates
Solution Approach 1:
The patent applies equipotentiality principle by arranging the VCO nodes and inverter units such that each node experiences equivalent electrical conditions. The symmetric configuration ensures that all nodes have the same number of inverter stages connected, creating equipotential conditions that result in uniform time delays across all phases. This approach ensures consistent phase delays despite layout variations.
Data Source
AI summary
A frequency doubler includes a voltage controlled oscillator outputting N (where, N is a natural number) signals having a first period and having different phases, and an XOR circuit receiving the N signals and outputting a signal having a second period that corresponds to a half of the first period, wherein the voltage controlled oscillator includes N nodes that correspond to the N signals and inverter units respectively connecting the N nodes, the N nodes are arranged so that, if a signal that starts from any one start node of the N nodes passes through the same number of the inverter units, it recurs to the corresponding start node, the XOR gate includes a first unit block set including N unit blocks that are connected to the same output node and match the N nodes in a one-to-one manner, and a second unit block set that is substantially the same as the first unit block set, wherein the first and second unit block sets share the output node.