Glitch-less Differential XOR Memory Architecture
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Solution Overview
Problem
Existing memory architectures for network processors with high memory bandwidth requirements are area-expensive and unsuitable for large capacity memories due to the use of large and costly multi-port memory bit-cells, which are not efficient in resolving address collisions during multi-read operations.
Innovation Solution
A high-bandwidth memory device employing a dynamic glitch-less differential XOR tree architecture, partitioned into multiple memory blocks with auxiliary sub-blocks to resolve address collisions through Boolean equations and XOR operations, reducing area usage and power consumption while enabling efficient multi-read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-port memory bit-cells are used to achieve high memory bandwidth, then read bandwidth is improved, but area cost increases significantly
Solution Approach 1:
The memory is divided into multiple banks, with each bank containing multiple sub-blocks. This segmentation allows parallel access to different banks while using simpler 1-port or 2-port memory bit-cells instead of complex multi-port bit-cells, thereby achieving high read bandwidth without proportionally increasing area cost.
Solution Approach 2:
The patent introduces a hierarchical structure with banks, sub-blocks, and auxiliary sub-blocks across multiple dimensions. Address collision resolution is achieved by distributing data across these dimensional hierarchies and using XOR operations to reconstruct original data, enabling multi-read capability without requiring multi-port bit-cells in each location.
2Adaptability or versatility
If multi-port memory bit-cells are used to resolve address collisions, then multi-read operation capability is improved, but device complexity increases
Solution Approach 1:
Instead of making each bit-cell multi-port to handle address collisions, the patent inverts the approach by making each bit-cell simple (1-port or 2-port) and using a system-level XOR tree architecture across multiple banks and sub-blocks to achieve the multi-read functionality. The complexity is moved from the bit-cell level to the architectural level.
Solution Approach 2:
The patent introduces auxiliary sub-blocks and XOR trees as intermediary structures between the simple memory bit-cells and the read ports. These intermediaries handle the address collision resolution and data reconstruction, allowing simple bit-cells to participate in complex multi-read operations without requiring multi-port capability.
3Quantity of substance
If existing bit-cells are used for large capacity memories, then memory capacity is improved, but area efficiency deteriorates
Solution Approach 1:
The patent designs a universal memory architecture where 1-port or 2-port bit-cells can be used across all banks and sub-blocks, regardless of the specific read operation requirements. The same simple bit-cell design is reused throughout the large capacity memory, and the multi-read capability is achieved through the external XOR tree architecture, improving area efficiency while maintaining large capacity.
Data Source
AI summary
A high-bandwidth multiple-read memory device includes multiple memory blocks, multiple address input buses, and a number of output data buses. The memory blocks include an auxiliary memory block and each memory block include several memory sub-blocks including an auxiliary memory sub-block. The output data buses output data corresponding to addresses corresponding to the address input buses during a multiple-read operation. The addresses correspond to a single memory sub-block of the memory sub-blocks of a memory block. Also described is differential XOR circuit that includes a selection logic circuit, a precharger circuit, and a multiplexer. The selection logic circuit provides a complementary output signal corresponding to a single-ended input signal. The multiplexer provides, during an evaluate phase, a differential output signal.