XOR Parity Circuit Reduction for Shorter ECC Data Paths
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Solution Overview
Problem
The integration of error correction codes in integrated circuits (ICs) increases data path length due to the large number of XOR logic operation units, leading to circuit complexity and computational inefficiencies.
Innovation Solution
Implement a method for parity bit calculation using a reduced set of XOR operation circuits based on parity bit coverage reduction, optimizing the error correction circuit to minimize critical path length and chip area while maintaining error correction capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all XOR operation circuits are configured for error correction, then error correction capability is improved, but circuit complexity increases
Solution Approach 1:
The patent extracts and removes redundant XOR operation circuits from the error correction circuit. By analyzing the parity bit coverage requirements, the invention identifies and eliminates unnecessary XOR circuits that do not contribute to the actual error correction capability for the given data width, thereby reducing circuit complexity while preserving error correction functionality.
Solution Approach 2:
The patent implements partial action by configuring only the necessary subset of XOR operation circuits required for the actual codeword length being processed. Instead of implementing all possible XOR circuits for maximum codeword length, the invention activates only those circuits needed for the specific data width, reducing overall circuit complexity while maintaining adequate error correction capability.
2Reliability
If more XOR operation circuits are used, then error correction coverage is improved, but chip area increases
Solution Approach 1:
The patent removes redundant XOR operation circuits that increase chip area without providing additional error correction coverage. By analyzing which XOR circuits are actually needed for the given data width and parity bit requirements, the invention extracts and eliminates unnecessary circuits, thereby reducing chip area while maintaining error correction coverage.
3Reliability
If all XOR operation circuits are configured, then comprehensive parity bit calculation is achieved, but data path length increases
Solution Approach 1:
The patent extracts and removes redundant XOR operation circuits that extend the data path without providing necessary error correction functionality. By identifying which XOR circuits are actually required for the specific codeword length and parity bit coverage needs, the invention eliminates unnecessary circuits from the data path, thereby reducing data path length while maintaining comprehensive parity bit calculation capability.
Data Source
AI summary
A method for performing parity bit calculation with aid of circuit complexity reduction for performing error correction and associated apparatus are provided. The method may include: in an error correction circuit adopting a predetermined error correction code, configuring a first set of exclusive OR (XOR) operation circuits among a plurality of XOR operation circuits corresponding to a predetermined codeword length, rather than all XOR operation circuits among the plurality of XOR operation circuits, for reducing circuit complexity of the error correction circuit, where the first set of XOR operation circuits may be a set of optimized XOR operation circuits implemented based on parity bit coverage reduction; and utilizing the first set of XOR operation circuits to perform the parity bit calculation, for performing error correction corresponding to a shorter codeword length, where a smaller XOR operation count and a shorter critical path length can be reached.