Weighted XOR Phase Detector With Phase Interpolation Feedback

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Solution Overview

Problem

High-speed chip-to-chip communication systems face challenges in accurately synthesizing a local receive clock signal due to varying signal propagation conditions, requiring advanced Clock Data Recovery (CDR) methods that can dynamically compensate for interference and noise.

Innovation Solution

The implementation of a dynamically-weighted XOR gate with configurable logic branches generates weighted segments of phase-error signals, producing an aggregate control signal to adjust the local oscillator's phase, enabling precise phase offset compensation and interpolation for accurate data sampling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a conventional XOR gate is used for phase detection, then the circuit complexity is low, but the phase detection precision and dynamic compensation capability are insufficient for high-speed communication

Engineering Contradiction:
Improvephase detection precisionVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The XOR gate is divided into multiple logic branches (first subset and second subset), each processing different portions of the phase error signal. This segmentation allows for weighted processing of phase detection results from different logic paths, improving precision while maintaining manageable circuit complexity through modular design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamically adjustable weights for different logic branches, allowing the phase detector to adapt its detection characteristics in real-time based on signal conditions. This dynamic weighting capability enhances phase detection precision under varying communication conditions without requiring a completely complex redesign of the basic XOR structure.

Inventive Principle:
Principle #15Dynamics

2Reliability

If dynamic phase compensation is implemented to compensate for varying signal propagation conditions, then the data sampling accuracy is improved, but the circuit complexity and computational overhead increase

Engineering Contradiction:
Improvedata sampling accuracyVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The phase detector generates an aggregate phase error signal that feeds back to control the local oscillator's phase. This feedback mechanism continuously compensates for signal propagation variations, improving data sampling accuracy and reliability while using a relatively simple feedback loop structure.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the phase parameter of the local oscillator dynamically based on the detected phase error. By adjusting the oscillator phase in response to detected errors, the system achieves reliable data sampling under varying conditions without requiring complex signal processing circuits.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If multiple logic branches with weighted segments are used to generate aggregate phase error signal, then the phase interpolation capability is enhanced, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvephase interpolation capabilityVSAvoidlogic branch weighting precision
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The phase error signal is divided into multiple weighted segments processed by different logic branches. Each branch handles a specific weight portion, and the aggregate signal combines these segments. This segmentation approach enhances phase interpolation capability while allowing standard manufacturing tolerances to be applied to each segment rather than requiring ultra-precise overall weighting.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10554380B2Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation
Publication Date: 2020.02.04 KANDOU LABS SA
  • US10554380B2 patent drawing
  • US10554380B2 patent drawing
  • US10554380B2 patent drawing

AI summary

Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.