XOR Quadrature Phase Detector With Offset Compensation
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Solution Overview
Problem
Existing quadrature phase detectors in high-speed communication systems suffer from inaccuracies due to device offsets caused by process variations in transistors, leading to incorrect phase detection even when clocks are in quadrature.
Innovation Solution
An XOR-gate based quadrature phase detector with circuitry designed to compensate for device offsets by using chopping sub-circuits and differential pairs to ensure accurate detection of quadrature phase relationships, providing a zero output when clocks are in perfect quadrature and a non-zero output when they are not.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an XOR-gate based quadrature phase detector is used to detect phase difference between quadrature clocks, then the detector can provide zero output when clocks are in perfect quadrature and non-zero output when there is phase error, but process variations in devices (transistors) cause the detector to provide incorrect output (zero output even when clocks are not in perfect quadrature, or non-zero output when clocks are in perfect quadrature)
Solution Approach 1:
The patent introduces chopping sub-circuits as intermediary elements between the differential pairs and the output. These chopping sub-circuits modulate the signals at a higher frequency, allowing the offset errors to be separated from the desired phase detection signal. The chopping action effectively transfers the offset errors to different frequency components that can be filtered out, thereby improving both measurement precision and reliability of the phase detector
Solution Approach 2:
The patent employs periodic chopping action at a frequency higher than the quadrature clock frequency. This periodic modulation allows the detector to average out the random offset errors caused by process variations over multiple cycles. By performing the detection over many periodic chopping cycles, the reliable output is achieved despite device variations
2Productivity
If two slower quadrature clock signals are used instead of a single fast clock to increase data rates, then data can be transferred at twice the speed at rising or falling edges of both quadrature clocks, but accurate phase relationship between the multiple phases of the quadrature clocks becomes essential and difficult to maintain due to device offsets
Solution Approach 1:
The patent implements a feedback mechanism where the phase detector continuously monitors the phase relationship between quadrature clocks and generates an error signal. This error signal is fed back to adjust the phase of the quadrature clocks, creating a closed-loop system that automatically corrects phase errors caused by device offsets, thereby maintaining accurate phase relationship for high-speed data transfer
Solution Approach 2:
The patent replaces direct physical phase alignment mechanisms with an electronic detection and correction system. Instead of relying on precise physical timing relationships that are sensitive to device variations, the system uses electronic phase detection with chopping sub-circuits and feedback control to dynamically maintain the required phase relationship, enabling reliable high-speed operation
Data Source
AI summary
A circuit includes a plurality of differential pairs of transistors and circuitry connected to the plurality of differential pairs of transistors. The plurality of differential pairs of transistors is configured to receive a first clock and a second clock and to generate an output representing an exclusive OR sum of the first and second clocks. The circuitry is configured to compensate for mismatch between the plurality of differential pairs of transistors so that the output is zero when the first and second clocks are in quadrature with each other and the output is non-zero when the first and second clocks are not in quadrature with each other regardless of mismatch between the plurality of differential pairs of transistors.