Combinatorial XOR Spreader for IC Test Coverage
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Solution Overview
Problem
The increased complexity of integrated circuits and modules makes thorough testing challenging, especially for untestable modules like RAM and analog components, due to random resistant faults that impact controllability and observability, and existing boundary-scan techniques are inadequate for providing complete test coverage without significant silicon area overhead.
Innovation Solution
A method involving a combinatorial XOR spreader circuit that generates N bits of test data from K bits, using multiplexors and flip-flops to provide test inputs, reduces the number of control scan flops required and minimizes area overhead while maintaining high test coverage by introducing randomization to break correlation effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If boundary-scan cells are used to replace physical probes for testing IC inputs and outputs, then physical access is no longer required and continuity test is no longer subject to IC complexity, but the number of pins required for test control and observation increases
Solution Approach 1:
The patent merges multiple test data bits into fewer pins by using a combinatorial circuit that takes K bits of test data and generates N bits where N > K. This allows multiple boundary-scan cells to be controlled and observed through fewer TDI and TDO pins, reducing pin overhead while maintaining full test capability.
Solution Approach 2:
The patent introduces a temporal dimension to the test data transmission by using shift register functionality. Test data is shifted in serially over time through fewer pins rather than requiring parallel access through more pins. The boundary-scan cells are clocked through test modes sequentially, allowing compact pin usage while maintaining full controllability and observability.
2Reliability
If modules containing random resistant faults are tested using traditional boundary-scan techniques, then test coverage is limited, but adding more test points increases silicon area overhead
Solution Approach 1:
The patent introduces combinatorial circuits as intermediary elements between the test data input and the boundary-scan cells. These intermediary circuits expand K bits of test data into N bits, providing enhanced controllability for testing modules with random resistant faults without requiring proportional increases in silicon area or pin count.
Solution Approach 2:
The patent changes the parameter relationship between test data input and output by using a combinatorial expansion where N > K. This parameter transformation allows a small number of input pins to control a large number of boundary-scan cells, achieving high test coverage for complex modules while minimizing the physical test interface requirements.
3Reliability
If the number of boundary-scan cells is increased to achieve thorough testing of complex integrated circuits, then test coverage improves, but the complexity of test control and observation increases
Solution Approach 1:
The patent combines multiple test data lines into fewer control lines by using a combinatorial circuit that expands K bits into N bits. This merging approach allows a small number of TDI pins to control a large number of boundary-scan cells, reducing the complexity of test control while maintaining comprehensive test coverage for complex integrated circuits.
Solution Approach 2:
The patent segments the test data transmission into serial shifts through the boundary-scan register chain. By dividing the test data into sequential bits that are shifted through the register chain one at a time, the system can control and observe many boundary-scan cells using fewer pins and simpler control logic, reducing overall test control complexity.
Data Source
AI summary
Described examples include a method of providing K bits of test data to a combinatorial circuit. The method further includes generating N bits of test data using the combinatorial circuit, where N is greater than K. The method further includes providing the N bits of test data to a module under test.