Complementary XOR SRAM Cell for Single-Cycle Full Adder Logic

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Solution Overview

Problem

Current static random access memory (SRAM) cells cannot perform certain logic functions, such as exclusive OR (XOR), which are essential for advanced computational operations like search operations and floating-point calculations, and they require multiple clock cycles for full adder operations, limiting their efficiency.

Innovation Solution

A CMOS implemented 3-port SRAM complementary XOR cell with two read bit lines that enables two logic computations per clock cycle, allowing for the performance of full adder operations in a single clock cycle by utilizing cross-coupled inverters and specific transistor configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional SRAM cells are used, then basic Boolean operations (AND, OR, NAND, NOR) can be performed, but certain logic functions like XOR cannot be implemented

Engineering Contradiction:

Improvelogic function capabilityVSAvoidcell structure

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent modifies the conventional SRAM cell to perform multiple logic functions including XOR, AND, OR, NAND, and NOR operations. By adding selective write capability and configuring the cross-coupled inverters and access transistors appropriately, a single cell type can execute diverse Boolean operations, eliminating the need for different specialized cell designs for each logic function.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent changes the operational parameters of the SRAM cell by introducing selective write modes and different read configurations. By controlling the write word line and bit line selections, the same physical cell structure can be configured to perform different logic operations, effectively changing its functional behavior without altering its physical design.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If conventional SRAM cells perform full adder operations, then computation can be done in memory, but it requires multiple clock cycles reducing efficiency

Engineering Contradiction:

Improvecomputation speedVSAvoidclock cycles

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent prepares the SRAM cell in advance by pre-charging the bit lines and configuring the internal state before the actual computation operation. This preliminary preparation allows the full adder operation to complete in a single clock cycle rather than requiring multiple sequential steps, as the cell is already positioned to execute the logic function immediately when activated.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent enables continuous computation operations by maintaining the cell in an active computational state throughout the clock cycle. The cross-coupled inverter configuration and selective write mechanism allow the cell to continuously perform logic operations without requiring intermediate stabilization phases, thereby reducing the total time needed for full adder operations.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS10958272B2Computational memory cell and processing array device using complementary exclusive or memory cells

Publication Date: 2021.03.23 GSI TECHNOLOGY INC

AI summary

A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.