Multi-Input XOR/XNOR Circuit Layout for Low-Area Fast Logic

Solution Overview

Problem

Conventional logic gates consume significant area on a chip and are slow in performance, necessitating improvements in area consumption, speed, and performance.

Innovation Solution

The development of optimized multi-input logic circuitry designs for XOR and XNOR logic gates, including 2-input and 3-input variants, which utilize specific transistor configurations to reduce area usage and enhance performance, allowing for smaller and faster logic gate implementations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If conventional logic gate designs are used, then area consumption is significant, but area usage can be reduced with optimized transistor configurations

Engineering Contradiction:

Improvearea usageVSAvoidtransistor configuration complexity

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The logic gate is divided into multiple stages (first stage, second stage, third stage) with each stage performing a specific function. The first stage includes first logic structures coupled in series, the second stage includes second logic structures coupled in parallel, and the third stage processes the combined signals. This segmentation allows for optimized area usage while maintaining clear functional separation and reducing overall complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from conventional two-dimensional planar transistor arrangements to a multi-stage three-dimensional configuration. By stacking logic structures in series and parallel across multiple stages, the design achieves better area efficiency while maintaining signal integrity and logical functionality.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Speed

If conventional logic gate designs are used, then performance is slow, but speed can be improved with optimized circuit stages

Engineering Contradiction:

Improveperformance speedVSAvoidcircuit stage complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The logic gate is divided into multiple stages (first stage, second stage, third stage) with each stage performing a specific function. The first stage includes first logic structures coupled in series, the second stage includes second logic structures coupled in parallel, and the third stage processes the combined signals. This segmentation allows for optimized area usage while maintaining clear functional separation and reducing overall complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from conventional two-dimensional planar transistor arrangements to a multi-stage three-dimensional configuration. By stacking logic structures in series and parallel across multiple stages, the design achieves better area efficiency while maintaining signal integrity and logical functionality.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10922465B2Multi-input logic circuitry

Publication Date: 2021.02.16 ARM LTD

AI summary

Various implementations described herein refer to an integrated circuit having multiple stages including a first stage, a second stage, and a third stage. The first stage has first logic structures coupled in series, and the first logic structures are activated with multiple signals. The second stage has second logic structures coupled in parallel, and the second logic structures are activated with the multiple signals. The third stage has a first input, a second input, and an output. The first input is coupled to the first stage, the second input is coupled to the second stage, and the output provides an output signal based on the multiple signals.