XOR-XNOR Compressor Circuit for Faster Partial Product Reduction
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Solution Overview
Problem
Current data compression techniques in logic circuits, particularly in multipliers and partial product adders, face challenges with high power consumption and processing speed due to the rate of partial product reduction, which affects circuit performance.
Innovation Solution
The implementation of an XOR-XNOR circuit that processes input data signals in parallel, reducing the delay and power consumption by generating XOR and XNOR output signals with less diffusion and using transistors configured in series and parallel configurations to optimize operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If standard XOR-based cells are used for partial product reduction, then the circuit can perform data compression, but the power consumption increases and processing speed decreases
Solution Approach 1:
The patent combines XOR and XNOR operations into a unified circuit structure that processes multiple partial products simultaneously. The compressor cell integrates multiple logic functions (XOR, XNOR, AND, OR) in a merged architecture that reduces the number of separate components needed, thereby reducing overall power consumption while maintaining processing throughput.
Solution Approach 2:
The patent introduces a new dimension of operation by implementing both XOR and XNOR outputs from the same input stage. This dimensional expansion allows the circuit to handle multiple partial product reduction paths in parallel, improving processing speed without proportionally increasing power consumption, as the additional functionality is achieved through clever logic sharing rather than simply adding more components.
2Speed
If partial product reduction is performed at high rate, then processing speed improves, but circuit performance is adversely impacted
Solution Approach 1:
The patent segments the partial product reduction process into distinct stages handled by specialized logic units. Rather than attempting to reduce all partial products in a single high-speed stage, the circuit divides the work into multiple manageable stages with controlled data flow, preventing signal congestion and maintaining signal integrity even at high processing rates.
Solution Approach 2:
The patent introduces intermediary logic stages that buffer and condition signals between the high-speed reduction stages and the final output. These intermediary elements act as mediators that prevent signal degradation and maintain circuit performance by providing controlled transitions between fast reduction operations and stable output generation.
3Productivity
If XOR operations are performed with high diffusion, then more partial products can be processed, but delay increases
Solution Approach 1:
The patent performs preliminary organization and grouping of partial products before they enter the XOR/XNOR reduction stages. By pre-processing the input data to arrange partial products in an optimal sequence and grouping, the circuit minimizes the number of diffusion steps required during reduction, thereby reducing delay while still maintaining the ability to process a high number of partial products.
Data Source
AI summary
A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.