Parallel XOR-XNOR Compressor Circuit for Low-Delay Multipliers
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Solution Overview
Problem
Existing data compressors face challenges in reducing partial product reduction delays and power consumption in multiplier circuits, which impact the speed and efficiency of data processing, particularly in graphics and machine learning applications.
Innovation Solution
The implementation of an XOR-XNOR circuit with specific transistor configurations and multiplexers in compressor cells, which processes XOR and XNOR operations in parallel, reducing delay and power consumption by generating output bit signals with less latency and lower power usage compared to standard XOR-based cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If standard XOR-based compressor cells are used, then the circuit can perform partial product reduction, but the delay and power consumption increase
Solution Approach 1:
The compressor cell is segmented into multiple parallel paths: an XOR path and an XNOR path. Each path processes different combinations of input signals simultaneously, dividing the original single-path processing into concurrent segments that complete faster when combined.
Solution Approach 2:
The invention adds a new dimension to the logic operation by introducing both XOR and XNOR operations in parallel. This transforms the single-dimension sequential processing into a multi-dimensional parallel processing structure, where multiple logic outcomes are generated simultaneously from the same inputs.
2Power
If standard XOR-based compressor cells are used, then the circuit can perform partial product reduction, but the power consumption increases
Solution Approach 1:
The power consumption is segmented across parallel paths where each path handles specific signal combinations. This allows the circuit to activate only the necessary paths for given inputs, reducing overall power usage compared to always-active standard XOR cells.
Solution Approach 2:
The compressor cell dynamically selects between XOR and XNOR paths based on input conditions. This dynamic adaptation allows the circuit to optimize power consumption by activating only the required logic path for each operation, rather than maintaining all paths in a static, always-on state.
3Loss of time
If more complex transistor configurations are used to reduce delay, then the circuit performance improves, but the device complexity increases
Solution Approach 1:
The complex transistor configuration is segmented into modular units with standardized structures. Each compressor cell contains repeating patterns of transistors arranged in systematic configurations, making the complexity manageable and reusable across multiple cells.
Solution Approach 2:
Multiple transistor functions are merged into integrated configurations where shared transistors serve multiple logic operations. The XOR and XNOR paths share common transistor structures and control signals, reducing the total transistor count compared to implementing separate independent logic gates.
Data Source
AI summary
A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.