X-Propagation Verification for Low Power SoC Isolation Logic
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Solution Overview
Problem
Current electronic design verification methods for low power designs, particularly in the EDA field, fail to effectively detect and address X-bugs due to hidden X-values during simulations, leading to costly and late-stage defects in Gate Level Simulation, especially in modern System-on-a-chip (SoCs) and low power logic verification.
Innovation Solution
A computer-implemented method for electronic design verification that identifies and tracks X-values at the Register Transfer Level (RTL) during simulations, ignoring inactive power domains and providing graphical user interface options to display and diagnose the cause of X-values, thereby enabling early detection of X-bugs in isolation logic and state retention using X-Propagation technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard HDL simulation semantics are used, then simulation speed is improved, but X-bugs are concealed and not detected
Solution Approach 1:
The patent applies preliminary action by performing X-propagation analysis during RTL simulation before gate-level simulation. The system proactively identifies potential X-bug sources by tracking X-value propagation paths in advance, allowing defects to be detected early in the verification cycle rather than waiting for slower gate-level simulation to reveal them.
Solution Approach 2:
The patent introduces an intermediary mechanism - the X-propagation analysis engine - that sits between the RTL simulator and the designer. This intermediary component intercepts simulation data, performs specialized X-value tracking and propagation analysis, and presents findings to the designer, thereby enhancing bug detection without requiring changes to the underlying RTL simulation semantics.
2Reliability
If gate level simulation is performed to detect X-bugs, then X-bug detection accuracy is improved, but verification time and cost increase
Solution Approach 1:
The system performs X-propagation analysis during RTL simulation as a preliminary step before gate-level simulation. By identifying and analyzing X-bug sources early in the verification flow, the patent reduces the reliance on time-consuming gate-level simulation for X-bug detection, thereby decreasing overall verification time while maintaining detection accuracy.
Solution Approach 2:
The patent extracts the X-bug detection function from the general-purpose gate-level simulation process and implements it as a separate, specialized X-propagation analysis that operates during RTL simulation. This extraction allows X-bug detection to be performed independently and earlier in the verification cycle, reducing the time burden of gate-level simulation.
3Reliability
If manual test bench elements are created to model isolation and state retention, then verification coverage is improved, but device complexity and effort increase
Solution Approach 1:
The patent applies self-service by enabling the RTL simulator to automatically perform X-propagation analysis and identify isolation/station retention bugs without requiring manual test bench elements. The system uses existing RTL simulation data and automatically traces X-value propagation paths, eliminating the need for designers to create complex manual test bench models while maintaining comprehensive verification coverage.
Solution Approach 2:
The X-propagation analysis engine serves multiple functions simultaneously: it tracks X-value propagation, identifies isolation logic bugs, detects state retention issues, and provides diagnostic information. This multi-functional approach replaces multiple specialized test bench elements with a single unified analysis mechanism, reducing test bench complexity while maintaining verification coverage.
Data Source
AI summary
The present disclosure relates to a computer-implemented method for electronic design verification. The method may include providing, using a processor, a low-power electronic design and determining if a power domain associated with the low-power electronic design is active. The method may further include identifying, at a register transfer level (RTL) at least one X value associated with an active power domain wherein identifying occurs during a simulation.