XPU Address Translation Cache Interface Bypassing IOMMU

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Solution Overview

Problem

Legacy systems face inefficiencies in utilizing Address Translation Service (ATS) of PCIe architecture, particularly due to the bottleneck caused by the IOMMU acting as a middle-man between system software and XPU-ATC, limiting performance and scalability.

Innovation Solution

An architectural interface is introduced that allows direct communication between system software and XPU-ATCs, bypassing the IOMMU, enabling parallel communication and reducing complexity, while also benefiting from link encryption for improved security.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the IOMMU acts as a middle-man between system software and XPU-ATC, then address translation can be performed, but system performance and scalability are limited due to the bottleneck

Engineering Contradiction:

Improvesystem performanceVSAvoidcommunication architecture complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts the IOMMU from the communication path between system software and XPU-ATC, removing it as an intermediate component. This allows direct communication between software and the address translation cache, eliminating the performance bottleneck while maintaining the address translation functionality through the software-managed ATC interface.

Inventive Principle:

Principle #2Taking out (Extraction)

2Adaptability or versatility

If the IOMMU acts as a middle-man, then address translation is enabled, but communication scalability is reduced

Engineering Contradiction:

Improvecommunication scalabilityVSAvoidcommunication architecture complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The IOMMU is removed from the communication architecture, allowing multiple XPUs to communicate directly with system software without being constrained by a single intermediate translation layer. This extraction enables improved scalability while the ATC interface maintains the necessary address translation capabilities.

Inventive Principle:

Principle #2Taking out (Extraction)

3Productivity

If direct communication between software and XPU-ATC is implemented, then performance and scalability are enhanced, but security may be compromised without link encryption

Engineering Contradiction:

Improvesystem performanceVSAvoidsecurity vulnerabilities

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces link encryption as a security intermediary that protects the direct communication channel between system software and XPU-ATC. This encryption layer ensures that the performance benefits of direct communication are maintained while security vulnerabilities are mitigated through cryptographic protection of the data in transit.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20220414020A1Software interface to XPU address translation cache

Publication Date: 2022.12.29 INTEL CORP

AI summary

In an embodiment, a core includes at least one execution circuit. The core may be configured to: send a command for a first address translation cache (ATC) of a first device to perform an operation, the core to send the command to a first device queue of a shared memory, the first device queue associated with the first ATC; and send a register write directly to the first device to inform the first ATC regarding presence of the command in the first device queue. Other embodiments are described and claimed.