Xtacking DRAM Memory Cell Architecture for Simpler Wafer Processing
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Solution Overview
Problem
As DRAM technology advances towards higher densities and capacities, the increased number and reduced size of capacitors lead to longer process times and more complex process flows, complicating the manufacturing of dynamic random access memory (DRAM) devices.
Innovation Solution
The Xtacking architecture, where capacitors are processed on an array wafer and periphery transistors and array transistors are processed on a separate periphery wafer, enabling electrical connection through metal Vertical Interconnect Accesses (VIAs) in a single process step, simplifying the process flow and reducing cycle time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If capacitors are processed on the same wafer as transistors using conventional DRAM manufacturing, then integration is achieved, but process time increases and process flow complexity increases
Solution Approach 1:
The patent divides the DRAM manufacturing process into two separate wafers: a first wafer for processing array transistors and a second wafer for processing capacitors. This segmentation allows parallel processing of different components, reducing overall process time and simplifying the process flow while maintaining full integration through subsequent bonding and electrical connection steps.
2Quantity of substance
If capacitor size is reduced to increase storage density, then storage capacity increases, but manufacturing complexity increases
Solution Approach 1:
By segmenting the manufacturing process into separate wafer processing for capacitors and transistors, the patent enables independent optimization of capacitor size and density without complicating the overall manufacturing process. The separated flow allows specialized processing for high-density capacitor arrays while maintaining manageable complexity through modular assembly.
3Quantity of substance
If more capacitors are integrated to increase storage capacity, then storage density increases, but process flow complexity increases
Solution Approach 1:
The patent implements segmentation by processing multiple capacitors on a dedicated second wafer separate from the transistor processing on the first wafer. This allows for scaled integration of numerous capacitors to increase storage capacity while maintaining a simple, modular process flow that can be easily replicated and assembled.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in higher storage density, a simpler process flow, and reduced cycle time, addressing the complexity and efficiency challenges in manufacturing DRAM devices.
Implementation Method 1
The bonding structures are configured to couple the array transistor to the capacitor structure to form a memory cell
Data Source
Figure 1A~2
Figure 3
Figure 4A
AI summary
A semiconductor device is provided. The semiconductor device includes a first wafer having an array transistor formed therein, and a second wafer having a capacitor structure formed therein. The semiconductor device also includes a bonding interface formed between the first wafer and second wafer that includes a plurality of bonding structures. The bonding structures are configured to couple the array transistor to the capacitor structure to form a memory cell.