Xtacking Pad-Out Structure Using Backside Contact Formation
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Solution Overview
Problem
The manufacturing process for pad-out structures in Xtacking architecture semiconductor devices is complex due to the need for deposition and etching of additional dielectric layers and through-silicon-contact (TSC) metals, which complicates the formation of pad-out structures.
Innovation Solution
A method for fabricating pad-out structures that eliminates the need for additional dielectric layers and TSC metals by bonding two dies face-to-face, forming contact holes, and patterning conductive layers on the back side of the first die to create pad-out structures, simplifying the process and reducing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional TSC configuration is used to form pad-out structures, then electrical connectivity is achieved, but the manufacturing process becomes complex due to deposition and etching of additional dielectric layers and TSC metals
Solution Approach 1:
The patent extracts and eliminates the complex TSC metal deposition and additional dielectric layer processing from the pad-out structure fabrication. Instead of using traditional TSC configuration with multiple material depositions, the invention uses a simplified approach where pad-out structures are formed by patterning the existing conductive layer (first conductive layer 171) directly after substrate removal, removing the disturbing complex processing steps while maintaining electrical connectivity functionality.
Solution Approach 2:
The patent inverts the traditional sequence by removing the substrate first and then forming pad-out structures from the exposed conductive layer, rather than forming TSC metals and dielectric layers before or during substrate processing. This inversion simplifies the process flow by utilizing the already-formed conductive layer (171) as the basis for pad-out structures, eliminating the need for additional metal deposition and dielectric layer etching steps.
2Ease of manufacture
If additional dielectric layers and TSC metals are deposited, then pad-out structures can be formed, but manufacturing cost increases
Solution Approach 1:
The patent discards the traditional approach of depositing additional TSC metals and dielectric layers. Instead, it recovers and utilizes the first conductive layer (171) that is already present in the structure after substrate removal, patterning it directly to form pad-out structures. This eliminates material costs associated with additional metal depositions and reduces manufacturing complexity.
Solution Approach 2:
The first conductive layer (171) serves multiple functions: it acts as both the original conductive interconnect layer and the material from which pad-out structures are formed. This multi-functionality eliminates the need for separate TSC metal deposition steps, reducing both material costs and process complexity while achieving the same electrical connectivity function.
3Ease of operation
If substrate is removed to expose contact structures, then pad-out structures can be formed on back side, but process complexity increases
Solution Approach 1:
The substrate is removed in advance before pad-out structure formation, exposing the first contact structure (121) and enabling direct access to the first conductive layer (171) on the back side of the first die (D1). This preliminary substrate removal simplifies subsequent pad-out structure formation by providing direct access to the conductive layer without requiring complex through-silicon-contact processing or additional dielectric layer etching.
Data Source
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AI summary
The present disclosure provides a method of fabricating a semiconductor device. The method can include bonding a first die and a second die face to face, the first die including a substrate, transistors formed on a face side of the first die over a semiconductor layer with an insulating layer between the substrate and the semiconductor layer, and a first contact structure on the face side of the first die extending through the insulating layer. The method can also include exposing the first contact structure from the back side of the first die, forming, from the back side of the first die, a contact hole in the insulating layer to expose the semiconductor layer, and forming, on the back side of the first die, a first pad-out structure connected with the first contact structure and a second pad-out structure, on the contact hole, conductively connected with the semiconductor layer.