Yield Learning Vehicle With Phased Design Windows
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Solution Overview
Problem
Current IC testing methods using yield learning vehicles (YLVs) are limited in their ability to effectively identify and address yield issues until production chips are manufactured, leading to inefficiencies in the yield ramp-up process due to the lack of sufficient testing observability and debug features for partially functional blocks.
Innovation Solution
The implementation of YLVs with varying and phased design window sizes, including a yield learning controller and bypasses, allows for increased testing observability and debug features by facilitating the testing of circuit blocks with different design window sizes, enabling more comprehensive feedback for IC design and fabrication adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional YLVs with uniform design window sizes are used, then manufacturing simplicity is maintained, but testing observability and debug capability are insufficient
Solution Approach 1:
The YLV is divided into multiple circuit blocks, each with different design window sizes (first design window size and second design window size). This segmentation allows different portions of the chip to be tested under different design conditions, improving overall testing observability without requiring a completely different YLV design for each test phase.
Solution Approach 2:
Different circuit blocks within the same YLV are assigned different design window sizes based on their specific testing requirements. This local differentiation enables targeted testing of specific blocks with appropriate design margins, enhancing debug capability for partially functional blocks while maintaining manufacturing efficiency.
2Reliability
If YLVs are redesigned for each testing phase, then comprehensive yield feedback is achieved, but fabrication time and costs increase
Solution Approach 1:
The YLV is pre-designed with multiple circuit blocks having different design window sizes before fabrication. This preliminary inclusion of varied design windows allows the same fabricated YLV to be used across multiple testing phases, eliminating the need for repeated redesigns and reducing fabrication time while maintaining reliable yield feedback.
Solution Approach 2:
A single YLV design serves multiple testing phases by incorporating circuit blocks with different design window sizes. This multi-functional approach allows the same physical chip to provide comprehensive yield information across different testing conditions, reducing both fabrication time and costs while improving yield feedback reliability.
3Ease of repair
If design window sizes are increased for better testing coverage, then debug capability improves, but chip area and manufacturing complexity increase
Solution Approach 1:
Instead of uniformly increasing design window sizes across the entire chip, the YLV segments different circuit blocks with different design window sizes. This allows debug capability to be enhanced only in specific blocks where it is most needed, rather than expanding the entire chip area.
Solution Approach 2:
Larger design window sizes are applied locally to specific circuit blocks that require enhanced debugging, while other blocks maintain standard design windows. This localized approach improves debug capability for critical blocks without proportionally increasing the overall chip area or manufacturing complexity.
Data Source
AI summary
Techniques for providing improved semiconductor yield learning are discussed herein. Some embodiments may include a yield learning vehicle (YLV), including a communication fabric and a plurality of circuit blocks connected with the communication fabric. The plurality of circuit blocks may include circuit blocks having different design window sizes, and may be configured to support different phases of a yield learning ramp up process. The YLV may further include a yield learning controller configured to control circuit block testing, and bypasses configured to partially or fully replicate the behavior of improperly functioning or untested circuit blocks. Some embodiments may include techniques for software implementation of the YLV, such as by invoking a computer to receive data representative of a design of the YLV, and based on the data representative of the design of the integrated circuit, causing the computer to generate data representative of YLV.