Yield-Relevant Parameter Identification in IC Fabrication
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Solution Overview
Problem
The complexity of integrated circuit fabrication processes makes it difficult to monitor and control process parameters effectively, leading to challenges in identifying yield-relevant parameters and optimizing device performance.
Innovation Solution
The development of a method involving the creation of test structures on wafers to collect process tool data, which is used to build models that relate defectivity data to yield, allowing for the identification of key process parameters impacting yield and optimizing the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If comprehensive process monitoring is implemented across all fabrication steps, then process control quality improves, but system complexity and difficulty of operation increase due to the large number of process parameters
Solution Approach 1:
The patent segments the large set of process parameters into two categories: yield-relevant parameters that significantly impact device outcomes and non-yield-relevant parameters. This segmentation allows monitoring efforts to be focused on the critical subset of parameters, reducing system complexity while maintaining process control quality.
Solution Approach 2:
The patent extracts and identifies the specific yield-relevant parameters from the comprehensive set of all process parameters through statistical analysis and correlation studies. By taking out only the essential parameters that drive yield, the system avoids the complexity of monitoring all parameters equally while preserving the ability to control manufacturing precision.
2Productivity
If all process parameters are monitored and controlled, then yield optimization potential improves, but the difficulty of detecting and measuring relevant parameters increases
Solution Approach 1:
The patent implements feedback mechanisms through statistical analysis that continuously monitor process parameters and correlate them with yield outcomes. This feedback loop identifies which parameters are yield-relevant by analyzing the relationship between parameter variations and device performance, making parameter identification systematic rather than trial-and-error.
Solution Approach 2:
The patent performs preliminary statistical analysis and correlation studies before full-scale production to pre-identify yield-relevant parameters. This preliminary action establishes which parameters warrant ongoing monitoring and control, reducing the difficulty of parameter detection during actual production while maintaining yield optimization potential.
Data Source
AI summary
In one embodiment, wafers are processed to build test structures in the wafers. The wafers may be processed in tools of process steps belonging to a process module. The test structures may be tested to obtain defectivity data. Tool process parameters may be monitored and collected as process tool data. Other information about the wafers, such as metrology data and product layout attribute, may also be collected. A model describing the relationship between the defectivity data and process tool data may be created and thereafter used to relate the process tool data to a yield of the process module. The model may initially be an initial model using process tool data from a limited number of test wafers that contain test structures. The model may also be an expanded model using process tool data from product wafers containing embedded test structures in areas with no product devices.