Ytterbium-Modified NiSi Gate Electrode for Work Function Tuning
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Solution Overview
Problem
The scaling down of semiconductor devices leads to polysilicon depletion issues in gate oxides, affecting device performance, and the formation of dual metal gates is complex, while achieving real band-edge work function modulation with fully silicided (FUSI) gate electrodes remains a challenge.
Innovation Solution
A method involving ytterbium (Yb) implantation in the nickel fully silicided (Ni-FUSI) process to reduce the work function of NMOS devices and decrease the equivalent oxide thickness (EOT) by forming a composite thin film between the FUSI gate electrode and the gate oxide layer, allowing for simplified integration and tunable work function.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon gates are used in scaled semiconductor devices, then device fabrication is simplified, but gate capacitance increases due to polysilicon depletion issues
Solution Approach 1:
The patent uses a composite gate structure consisting of a metal layer (such as tungsten, molybdenum, or titanium) combined with a silicide layer (such as nickel silicide or cobalt silicide). This composite material approach allows the gate to achieve both the low capacitance of metal gates and the ease of fabrication similar to polysilicon gates, while eliminating polysilicon depletion effects.
Solution Approach 2:
The patent changes the material parameters of the gate electrode by transitioning from polysilicon to metal-silicide composites. This parameter change includes modifying the work function, electrical conductivity, and capacitance characteristics to improve device performance while maintaining fabrication simplicity through standardized processing techniques.
2Reliability
If dual metal gates are formed for NMOS and PMOS transistors, then work function modulation is achieved, but formation and integration complexity increases
Solution Approach 1:
The patent segments the gate formation process into distinct stages: first forming a common metal layer for both NMOS and PMOS, then selectively forming silicide layers in specific regions. This segmentation allows different work functions to be achieved for NMOS and PMOS devices while using a simplified sequential process rather than requiring completely separate dual-metal gate formation procedures.
Solution Approach 2:
The patent performs preliminary formation of the metal gate layer across the entire device structure before selective silicidation. This preliminary action establishes a common foundation that simplifies subsequent processing steps and reduces integration complexity compared to forming different metal gates simultaneously or in reverse sequence.
3Ease of manufacture
If fully silicided gate electrodes are formed using rapid thermal annealing, then integration is simplified, but real band-edge work function modulation is difficult to achieve
Solution Approach 1:
The patent maintains continuous control over the silicidation process by using multiple rapid thermal annealing steps with varying temperatures and durations. This continuous action approach allows precise tuning of the silicide phase formation and interfacial properties, enabling real band-edge work function modulation while keeping the integration process simple and compatible with existing manufacturing workflows.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The Yb implantation effectively reduces the work function to reach the NMOS band edge and decreases EOT, with the mechanism involving Yb pile-up at the NiSi/dielectric interface and reaction with the gate electrode, resulting in improved device performance with minimal gate oxide leakage increase.
Implementation Method 1
The second metal layer reacts with the exposed polysilicon layer to form fully silicided (FUSI) gate electrode
Implementation Method 2
The second metal layer reacts with the exposed polysilicon layer to form fully silicided (FUSI) gate electrode
Implementation Method 3
The first metal layer reacts with the source/drain to form source/drain salicide
Implementation Method 4
The first metal layer reacts with the source/drain to form source/drain salicide
Implementation Method 5
A blanket ion implantation process is carried out to implant dopant species into the polysilicon layer
Data Source
AI summary
A semiconductor MOS device includes a semiconductor substrate; a gate oxide layer disposed on the semiconductor substrate; a fully silicided gate electrode disposed on the gate oxide layer; a composite thin film interposed between the fully silicided gate electrode and the gate oxide layer; a spacer on sidewall of the fully silicided gate electrode; and a source/drain region implanted into the semiconductor substrate next to the spacer. A method for forming the semiconductor MOS device is disclosed.