Z-Culling Method Using Exclusive Cache for 3D Graphics

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Solution Overview

Problem

Current Z-culling techniques in 3D graphics processing require frequent access to system memory, leading to high bandwidth usage and computational complexity due to the need for extensive calculations and comparisons, which hampers graphics processing speed, especially in complex 3D scenes.

Innovation Solution

Implementing an exclusive Z cache memory to reduce read and write frequency on the system memory by buffering cover masks and dynamic depth values, allowing for more efficient Z-culling operations and minimizing bandwidth usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If Z-buffering technique is used to manage image depth coordinates, then depth information is accurately maintained, but system memory bandwidth consumption increases significantly

Engineering Contradiction:
Improvedepth information accuracyVSAvoidsystem memory bandwidth consumption
Core Design Contradiction:
Measurement precisionVSLoss of energy

Solution Approach 1:

The patent extracts the Z-buffer from system memory and places it in the GPU's internal memory space. This separation removes the bandwidth bottleneck by eliminating frequent memory accesses while preserving the depth buffering functionality for accurate depth information management during rendering operations.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces an intermediary buffer structure within the GPU that acts as a mediator between depth calculation operations and the final Z-buffer storage. This intermediary mechanism reduces direct system memory accesses by performing depth comparisons and buffer updates within the GPU's internal memory hierarchy.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of energy

If coarse Z-culling technique is used to reduce Z-buffer access frequency, then memory bandwidth is reduced, but computational complexity and hardware implementation difficulty increase

Engineering Contradiction:
Improvememory bandwidth usageVSAvoidcomputational complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent segments the rendering process into distinct phases: geometry processing, depth buffer updates, and visibility determination. By dividing the complex Z-culling operation into manageable segments handled by dedicated GPU units, the patent reduces overall computational complexity while maintaining effective memory bandwidth management.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements self-service mechanisms where the GPU automatically manages depth buffer updates and visibility determinations through hardware-accelerated operations. This eliminates the need for complex software-based culling algorithms, reducing computational complexity while maintaining low memory bandwidth usage through efficient hardware-level depth testing.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9019271B2Z-culling method, three-dimensional graphics processing method and apparatus threrof
Publication Date: 2015.04.28 VIA TECH INC
  • US9019271B2 patent drawing
  • US9019271B2 patent drawing
  • US9019271B2 patent drawing

AI summary

A Z culling method, a three-dimensional graphics processing method using Z-culling, and an apparatus thereof are provided. The Z-culling method includes the following steps. A Z cache memory is provided to buffer a cover mask and a dynamic maximum depth value corresponding to each tile. A draw mask, a draw maximum depth value, and a draw minimum depth value calculated according to the tile and a drawn part are obtained. Moreover, whether the drawn part is completely included in a known part of the cover mask is judged, and coordinated with a comparison of the draw minimum depth value and the dynamic maximum depth value, so as to determine whether to discard the drawn part and whether to update the cover mask and the dynamic maximum depth value in the Z cache memory. Accordingly, the bandwidth taken up in the system memory is reduced efficiently.