Zener Diode Layout for Lower Leakage and Higher Breakdown Voltage
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Solution Overview
Problem
Existing IC fabrication methods face challenges in balancing tradeoffs between device types, such as Zener diodes and LDMOS transistors, leading to inefficient adjustments that affect targeted operational parameters like breakdown voltage and leakage current.
Innovation Solution
A method for forming an integrated circuit that includes forming a polysilicon layer and resist layers over a semiconductor substrate, creating diode wells and terminals with specific conductivity types, and using polysilicon as a hard mask to form diode structures, allowing for concurrent processing of Zener diodes and LDMOS transistors without additional steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If baseline manufacturing methods are used to form Zener diodes and LDMOS transistors separately, then each device can be optimized independently, but additional fabrication steps are required and manufacturing efficiency decreases
Solution Approach 1:
The patent combines the formation of Zener diodes and LDMOS transistors into a single integrated fabrication process. The polysilicon layer is formed once and serves dual purposes: as a hard mask for defining both diode regions and transistor regions. Subsequent ion implantation steps simultaneously create diode wells and transistor structures, eliminating the need for separate fabrication sequences and reducing overall process complexity.
Solution Approach 2:
The polysilicon layer performs multiple functions in the fabrication process. It serves as a hard mask for pattern transfer, defines the geometry of both diode and transistor regions, and enables self-aligned ion implantation for both device types. This multi-functional approach reduces the number of separate fabrication steps required.
2Reliability
If adjustments are made to optimize LDMOS transistor performance, then transistor power handling improves, but Zener diode operational parameters such as breakdown voltage and leakage current are adversely affected
Solution Approach 1:
The patent applies local quality by creating spatially distinct regions with different doping characteristics. The ion implantation process uses the polysilicon hard mask to define separate diode regions and transistor regions, allowing each to receive tailored doping profiles. Diode regions receive implantation optimized for Zener breakdown characteristics, while transistor regions receive doping optimized for power handling, thereby resolving the parameter tradeoff.
Solution Approach 2:
The fabrication process segments the substrate into distinct diode regions and transistor regions using the polysilicon layer as a patterned mask. This segmentation allows independent optimization of each device type within the same fabrication run, as ion implantation parameters can be selectively adjusted for different spatial zones without affecting the other device type.
3Manufacturing precision
If additional fabrication steps are added to optimize Zener diode parameters, then diode breakdown voltage and leakage current improve, but manufacturing time and cost increase
Solution Approach 1:
The polysilicon hard mask is formed in advance and serves as a pre-established pattern template for subsequent ion implantation steps. This preliminary action enables self-aligned fabrication, where the mask geometry automatically defines the precise location and dimensions of both diode and transistor regions, eliminating the need for additional alignment and patterning steps that would otherwise be required to achieve precise Zener diode parameters.
Data Source
AI summary
A method forms an integrated circuit, by steps including forming a polysilicon layer having a first side over a semiconductor substrate having a top surface, forming over the semiconductor substrate a first resist layer having a second side spaced apart from the first side, forming a diode well extending into the semiconductor substrate between the first side and the second side, the diode well having a first conductivity type, forming over the semiconductor substrate a second resist layer having a third side, and forming a diode terminal extending into the semiconductor substrate between the first side and the third side, the diode terminal having an opposite second conductivity type and extending from the diode well along the top surface.