Zener Triggered SCR With Integrated Junction Doping
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Solution Overview
Problem
Conventional Zener-triggered silicon controlled rectifiers (SCR) devices consume a large silicon area and have a lower current discharge capacity per unit area, limiting their application in nanoscale CMOS technology due to the high triggering voltage and additional implanted regions required for enhanced ESD efficiency.
Innovation Solution
A semiconductor device with a P-type substrate, N-well, and P-well structure that includes a Zener diode formed by alternately disposed N+ and P+ doped regions within the junction region between the N-well and P-well, eliminating the need for an additional P+ implanted region outside the junction and reducing silicon surface area while improving turn-on speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional Zener-triggered SCR devices use additional N+ and P+ implanted regions to enhance ESD efficiency, then the triggering voltage is improved, but the silicon surface area increases and current discharge capacity per unit area decreases
Solution Approach 1:
The patent merges the Zener diode structure with the SCR device by integrating the N+ and P+ implanted regions directly within the junction region between the N-well and P-well. This consolidation eliminates the need for separate additional implanted regions, thereby reducing silicon surface area while maintaining the ESD enhancement function through the combined structure's interaction during ESD events.
2Speed
If conventional Zener-triggered SCR devices integrate a Zener diode to speed up turn-on time, then the triggering speed is improved, but the device complexity and silicon area increase
Solution Approach 1:
The Zener diode is merged with the SCR device structure by placing the N+ and P+ implanted regions within the existing junction region. This integration allows the Zener diode to share physical space with the SCR components, thereby achieving fast triggering without proportionally increasing device complexity or silicon area.
Solution Approach 2:
The integrated structure serves multiple functions: the N+ and P+ implanted regions function as both the Zener diode for fast triggering and as part of the SCR's junction structure for current conduction. This multi-functionality reduces the need for separate dedicated structures, thereby limiting the increase in device complexity while maintaining turn-on speed improvement.
3Reliability
If conventional Zener-triggered SCR devices add implanted regions to reduce holding voltage, then the ESD protection capability is improved, but the current discharge capacity per unit area is reduced
Solution Approach 1:
The patent combines the ESD protection function with the current discharge function in a single integrated structure. The N+ and P+ implanted regions within the junction region simultaneously provide the low holding voltage needed for ESD protection and maintain adequate current discharge capacity by utilizing the existing junction geometry rather than adding separate dedicated regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the silicon surface area and enhances the turn-on speed of the SCR device, providing improved ESD protection without increasing manufacturing complexity or costs, making it compatible with conventional semiconductor processes at technology nodes below 40 nm.
Implementation Method 1
the Zener diode turns on first, causing a current flowing through the P-well of the SCR device, and ultimately turning on the SCR device through the voltage drop in the resistance of the P-well
Data Source
AI summary
A semiconductor device includes a P-type semiconductor substrate, an N-well and a P-well disposed adjacent to each other and extending along a first direction within the P-type semiconductor substrate, a first N+ doped region and a first P+ doped region extending along the first direction within the N-well and spaced away from each other along a second direction perpendicular to the first direction, a second N+ doped region and a second P+ doped region extending along the first direction within the P-well and spaced away from each other along the second direction, and a plurality of third N+ doped regions and a plurality of P+ doped regions alternatively disposed in a junction region formed between the N-well and P-well the third N+ doped regions. The third N+ doped regions and the third P+ doped regions form a Zener diode.