Zero-Cross Detection Circuit for Ultra-Low Power DC-DC Converters

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Solution Overview

Problem

Existing DC-DC converters in ultra-low power applications face inefficiencies due to inaccurate zero cross detection, leading to negative inductor current flow and increased power consumption, particularly in discontinuous conduction mode (DCM), which affects the precision and efficiency of the converter operation.

Innovation Solution

A control circuitry for zero cross detection in DC-DC converters that includes a peak detection circuit to generate a clock signal based on drain voltage peaking, a D flip-flop to generate digital output signals, and a zero cross detector to accurately determine the zero crossing of the inductor current, using low-power components like comparators, high-value resistors, or current sources to minimize power dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a comparator is used to detect zero crossing, then detection accuracy is improved, but power consumption increases

Engineering Contradiction:
Improvezero crossing detection accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent replaces the expensive high-power comparator with inexpensive, low-power alternatives such as high-value resistors and current sources that consume only nano-amps of current. These simpler components achieve sufficient detection accuracy without the continuous high power consumption of operational comparators, directly resolving the contradiction between detection accuracy and power consumption in ultra-low power DC-DC converters

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent changes the detection parameter from voltage comparison (requiring high-power comparators) to current-based detection using high-value resistors and current sources. By monitoring voltage drops across high-value resistors and comparing them against reference voltages generated by current sources, the system achieves zero-crossing detection with dramatically reduced power consumption while maintaining adequate accuracy for DCM operation

Inventive Principle:
Principle #35Parameter changes

2Loss of energy

If high-side switch is deactivated early to prevent negative current, then efficiency is improved, but zero crossing detection accuracy deteriorates

Engineering Contradiction:
Improveconverter efficiencyVSAvoidzero crossing detection accuracy
Core Design Contradiction:
Loss of energyVSMeasurement precision

Solution Approach 1:

The patent implements a feedback mechanism where the detection circuit continuously monitors the inductor current status and provides real-time feedback to the control logic. The high-value resistor network and current source-based detection continuously track the current waveform, enabling the control system to precisely determine when zero crossing occurs and adjust the high-side switch deactivation timing accordingly, preventing both early and late switching that would reduce efficiency

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent introduces high-value resistors as intermediary sensing elements that convert the inductor current information into measurable voltage drops without significantly loading the circuit. These resistors act as mediators between the inductor current and the detection logic, providing accurate zero-crossing information while consuming minimal power and not interfering with the normal operation of the high-side switch

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20260081512A1Control Circuitry for Zero Cross Detection In Ultra-Low Power DC-DC Converters
Publication Date: 2026.03.19 GREEN PMU SEMI PTE LTD
  • US20260081512A1 patent drawing
  • US20260081512A1 patent drawing
  • US20260081512A1 patent drawing

AI summary

A control circuitry for zero cross detection of inductor current (IL) is disclosed. The control circuitry includes an inductor, an nMOS low-side transistor switch and a pMOS high-side transistor switch. The control circuitry includes a peak detection circuit connected to the pMOS high-side transistor switch and configured to detect peaking of a drain voltage (VD) of the high-side transistor switch and generate a clock signal (CLK) if the drain voltage (VD) peaking is detected in an inductor current cycle. The control circuitry includes a D flip-flop connected to the peak detection circuit and operable based on the clock signal (CLK) generated by the peak detection circuit. The control circuitry includes a zero cross detector circuit coupled to the D flip-flop and the high-side transistor switch to detect zero crossing of the inductor current.