Zero Current Detecting Circuit for Synchronous Power Converters
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Solution Overview
Problem
Existing synchronous switching power converters face inefficiencies due to inaccurate detection of zero current on inductors, leading to conduction and switching losses, as offset voltages in comparators hinder precise timing for turning off the down-bridge transistor.
Innovation Solution
A zero current detecting circuit with two comparators and a counter system that adjusts delay times to compensate for offset voltages, ensuring accurate detection of zero current and precise timing for turning off the down-bridge transistor, comprising a first zero current comparator for determining current variation, a second comparator for assessing timing accuracy, and an adjustable delay unit to fine-tune the zero current signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single comparator measures voltage across resistor RS to detect zero current, then the detection circuit is simple, but offset voltage causes inaccurate timing for turning off the down-bridge transistor
Solution Approach 1:
The detection function is segmented into two independent comparators: the first comparator detects when inductor current reaches zero, and the second comparator verifies the accuracy of this detection by checking if the down-bridge transistor was turned off at the correct moment. This segmentation allows each comparator to have a specialized function, improving overall detection accuracy while maintaining reasonable circuit complexity.
Solution Approach 2:
The second comparator provides feedback about the timing accuracy to the control circuit. When the second comparator detects that the down-bridge transistor was turned off too early or too late, it generates a feedback signal that allows the system to adjust the turn-off timing, thereby compensating for offset voltage effects and improving measurement precision.
Data Source
AI summary
A zero current detecting circuit is disclosed. The zero current detecting circuit includes a first zero current comparator for determining current variation on an inductor of a synchronous switching power converter so as to output a zero current signal to turn off a down-bridge transistor of the synchronous power converter; a second zero current comparator for determining whether the first zero current comparator turns off the down-bridge transistor too early or too late and outputting a comparison result; a counter coupled to the second zero current comparator for ascending or descending a control bit according to the comparison result, and an adjustable delay unit coupled to the first zero current comparator and the counter for adjusting a delay time according to the control bit, and delaying and outputting the zero current signal according to the delay time, to compensate a negative offset voltage by delay.