Zero-Current Detector Offset Cancellation Circuit
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Solution Overview
Problem
Existing zero-current detectors (ZCDs) in synchronous buck converters are susceptible to silicon differences and offsets, leading to erroneous switch control in voltage converters, which can corrupt the output voltage.
Innovation Solution
A zero-current detector with a comparator, offset cancellation circuit, delay circuit, and auto-zero switch is introduced, enabling offset cancellation and a delay period to accurately detect zero current, while a reset circuit handles glitches to ensure reliable ZCD signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a zero-current detector is used in synchronous buck converters, then switch control accuracy is improved, but the detector becomes susceptible to silicon differences and offsets causing erroneous control
Solution Approach 1:
The patent applies preliminary action by performing offset sampling during the SW_ON period before the actual zero-current detection occurs. The offset cancellation circuit samples the comparator offset when the auto-zero switch is closed, storing this offset value for subsequent cancellation during the detection phase. This preliminary offset measurement enables accurate zero-current detection despite silicon variations and temperature drift.
Solution Approach 2:
The patent implements feedback through the offset cancellation circuit that continuously monitors and compensates for comparator offset. The circuit samples the offset during SW_ON, processes this information, and applies cancellation during the zero-current detection phase. This feedback mechanism ensures that offset variations due to silicon differences and temperature changes are continuously corrected, maintaining reliable switch control.
2Measurement precision
If offset cancellation is implemented to eliminate comparator offsets, then detection accuracy is improved, but circuit complexity increases
Solution Approach 1:
The patent merges the offset sampling and cancellation functions into a single integrated offset cancellation circuit. The circuit combines the auto-zero switch, sampling capacitors, and cancellation pathways into one unified block that performs multiple functions: offset sampling during SW_ON, offset storage, and offset cancellation during detection. This merging approach reduces overall circuit complexity compared to having separate circuits for each function.
Solution Approach 2:
The offset cancellation circuit is designed with multi-functionality, serving as both a sampling circuit during SW_ON and a cancellation circuit during zero-current detection. The same circuit components (capacitors, switches, amplifiers) are reused for different purposes at different times, eliminating the need for dedicated separate circuits and thereby reducing overall device complexity while maintaining offset cancellation capability.
3Speed
If the comparator continuously monitors current to detect zero current, then response speed is improved, but false detection due to glitches increases
Solution Approach 1:
The patent applies preliminary action by implementing a delay circuit that introduces a controlled time delay after the SW_OFF signal before enabling the comparator for zero-current detection. This delay allows transient glitches from the switching event to settle before the comparator begins monitoring, preventing false detections while maintaining fast response to actual zero-current conditions. The delay period is optimized to filter glitches without significantly delaying legitimate zero-current detection.
Data Source
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AI summary
A method for detecting zero-current of a voltage converter includes resetting a comparator output during a first period when a power switch of the voltage converter is turned on, and receiving, by an offset cancellation circuit, sample signals from the comparator. The method also determines a comparator offset using the sample signals. In response to an output voltage of the voltage converter being less than a threshold voltage, the comparator output is reset during a second period when the power switch is turned off. The comparator compares a first signal from the voltage converter with a second signal representing a ground voltage to generate a ZCD signal indicative of a comparison of the first and second signals. Then, an offset cancellation signal indicative of the determined comparator offset is generated to cancel the comparator offset.