Zero Cycle Clock Invalidate Operation for Multi-CPU Cache Coherence
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Solution Overview
Problem
In multi-processor systems, block invalidate operations can cause delays as they require iterating through the entire cache memory to ensure data coherence, leading to potential access of outdated data if not all cache lines are invalidated before new data is updated.
Innovation Solution
Implementing a range check during CPU access to treat cache hits within the block invalidate range as cache misses, ensuring data is retrieved from main memory without waiting for the block invalidate operation to complete, by marking cache lines as invalid if they fall within the invalidate range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a block invalidate operation iterates through the entire cache memory to ensure data coherence, then data coherence is maintained, but access delay increases
Solution Approach 1:
The patent initiates the block invalidate operation in advance without waiting for it to complete before allowing CPU accesses. The invalidate operation runs asynchronously in the background while CPU accesses proceed normally, and the range check mechanism ensures that any accesses within the invalidate range are treated as misses. This preliminary action approach eliminates the need to wait for invalidate completion, resolving the contradiction between maintaining data coherence and avoiding access delay.
Solution Approach 2:
The patent introduces a range check mechanism as an intermediary between the CPU access and cache hit/miss determination. This intermediary checks whether the accessed address falls within the block invalidate range and treats such accesses as misses even if the cache line appears valid. This mediator ensures data coherence without requiring the CPU to wait for the invalidate operation to complete, thus resolving the time delay issue.
2Reliability
If the CPU waits for block invalidate operation to complete before accessing data, then data accuracy is ensured, but productivity decreases
Solution Approach 1:
The block invalidate operation is performed as a preliminary background action that does not block CPU execution. The CPU continues to execute instructions and access memory while the invalidate operation progresses independently. The range check mechanism ensures data accuracy by treating accesses within the invalidate range as misses, allowing the CPU to maintain high throughput without waiting for invalidate completion.
Solution Approach 2:
The patent enables continuous CPU operation during the block invalidate process. Instead of pausing CPU execution to wait for invalidate completion, the system allows CPU accesses to continue uninterrupted. The range check mechanism operates continuously alongside the invalidate operation, ensuring that data accuracy is maintained while CPU productivity is preserved through uninterrupted execution.
3Speed
If a cache hit is returned immediately without checking invalidate status, then access speed is improved, but data coherence is compromised
Solution Approach 1:
The range check mechanism serves as an intermediary layer between the cache hit determination and the final data return. When a CPU access occurs, the system first checks whether the address falls within the block invalidate range. If it does, the access is treated as a miss regardless of cache validity bits. This intermediary check ensures data coherence is maintained while adding minimal overhead to access speed.
Solution Approach 2:
The cache system performs self-service by automatically checking the invalidate range during the cache access process. The range check is integrated into the cache control logic, allowing the system to self-determine whether an access should be treated as a hit or miss without external intervention. This self-service approach maintains data coherence while preserving fast access paths for valid cache hits.
Data Source
AI summary
A method to eliminate the delay of a block invalidate operation in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. A range check is performed on each CPU access while a block invalidate operation is in progress, and an access that maps to within the address range of the block invalidate operation is treated as a cache miss to ensure that the requesting CPU will receive valid data.