Zero-Data Memory Compression in Cache Directory Coherency
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Solution Overview
Problem
In multi-node computer systems, writing zero data to main memory can lead to inefficient use of cache directory entries and increased memory and bus bandwidth usage due to the need for cache directory lookups and probe requests, especially in applications involving memory erasures or data sparsity.
Innovation Solution
Implement a coherency management device that utilizes cache directory entries to indicate zero data through bits or spare states, allowing zero data to be returned without actual memory access, thereby optimizing cache directory usage and reducing bandwidth requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache directory lookups and probe requests are performed for zero data writes, then coherency management is maintained, but memory and bus bandwidth usage increases
Solution Approach 1:
The patent extracts zero data from the normal cache directory lookup and probe request process. When zero data is detected in the write data, the system skips the cache directory lookup and probe request steps entirely, directly writing the zero data to the cache without involving the coherency management device, thereby eliminating unnecessary bandwidth consumption while maintaining coherency for non-zero data
Solution Approach 2:
The patent inverts the traditional approach by treating zero data differently from normal data. Instead of processing zero data through the standard coherency management path, the system detects zero data and routes it through a simplified path that bypasses the coherency management device, effectively inverting the normal data flow logic to optimize for this specific case
2Loss of energy
If cache directory entries are used for zero data indication, then bandwidth usage is reduced, but cache directory entry availability decreases
Solution Approach 1:
The patent changes the state parameter of cache directory entries by introducing a zero data indication bit. This parameter change allows the same cache directory entry structure to serve dual purposes: tracking normal cache lines and indicating zero data writes, thereby reducing bandwidth usage without requiring additional cache directory entries
Solution Approach 2:
The patent makes cache directory entries multi-functional by enabling them to indicate both normal data presence and zero data writes. The cache directory entries serve multiple functions: tracking cache line validity, indicating zero data status, and maintaining coherency information, thereby maximizing the utility of existing cache directory resources
3Adaptability or versatility
If zero data is written to main memory, then data sparsity is handled, but memory bandwidth is wasted
Solution Approach 1:
The patent performs preliminary detection of zero data in the write data before the write operation completes. By detecting zero data early in the process, the system can take preliminary action to skip unnecessary memory bandwidth consumption steps, directly writing zero data to cache without performing cache directory lookups or probe requests that would consume memory bandwidth
Data Source
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AI summary
A coherency management device receives requests to read data from or write data to an address in a main memory. On a write, if the data includes zero data, an entry corresponding to the memory address is created in a cache directory if it does not already exist, is set to an invalid state, and indicates that the data includes zero data. The zero data is not written to main memory or a cache. On a read, the cache directory is checked for an entry corresponding to the memory address. If the entry exists in the cache directory, is invalid, and includes an indication that data corresponding to the memory address includes zero data, the coherency management device returns zero data in response to the request without fetching the data from main memory or a cache.