Zero Data Gating in Multiply-Accumulate Units
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Solution Overview
Problem
Current machine learning processing technologies, particularly in deep neural networks, face inefficiencies due to the need to perform multiply and accumulate operations even when input values are zero, leading to unnecessary power consumption and resource usage, especially in convolutional neural networks where many values are zero.
Innovation Solution
Implementing a technique called 'multiply-accumulate "0" data gating, where operations are gated or skipped when input values are zero, using methods such as power of two handling, shift registers, and clock gating to reduce power consumption and resource usage by only processing non-zero values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If multiply and accumulate operations are performed for all input values including zeros, then complete computational accuracy is maintained, but power consumption increases and processing efficiency decreases
Solution Approach 1:
The patent extracts and removes zero-valued operations from the computational pipeline. By detecting zero inputs and skipping the multiply-accumulate operations for these values, the system eliminates unnecessary computational steps while maintaining the accuracy of non-zero operations. This extraction of harmful zero operations directly reduces power consumption without compromising processing efficiency for meaningful data.
Solution Approach 2:
The patent applies partial action by performing multiply-accumulate operations only on non-zero input values rather than all inputs. The system selectively applies computational resources to only those operations that contribute to the final result, avoiding excessive computation on zero values. This partial execution strategy optimizes the balance between energy consumption and processing throughput.
2Reliability
If multiply and accumulate operations are performed on all input values, then computational completeness is ensured, but resource usage increases unnecessarily
Solution Approach 1:
The patent extracts zero operations from the computational flow and removes them from execution. By identifying and eliminating operations with zero inputs, the system maintains computational completeness for all non-zero values while reducing overall resource consumption. This extraction ensures that only necessary computational resources are allocated to meaningful operations.
Solution Approach 2:
The patent applies local quality by treating different input values differently based on their characteristics. Zero values receive a special treatment (skipping operations) while non-zero values receive full computational processing. This localized differentiation optimizes resource allocation by applying appropriate computational effort only where needed, rather than uniformly processing all inputs.
3Loss of energy
If operations are skipped for zero values, then power consumption and resource usage are reduced, but additional logic is required to detect and gate operations
Solution Approach 1:
The patent implements local quality by adding detection logic specifically at the points where zero values need to be identified and gated. Rather than complicating the entire computational architecture, the gating mechanism is localized to the input stage of the multiply-accumulate operations. This targeted approach minimizes the additional complexity required to achieve energy savings.
Solution Approach 2:
The patent introduces an intermediary gating mechanism that sits between the input data and the multiply-accumulate operation. This intermediary layer detects zero values and controls whether operations are executed, acting as a mediator that enables selective computation. The gating logic serves as a simple intermediary that adds minimal complexity while enabling significant energy reductions.
Data Source
AI summary
In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.


