Zero Diffusion Break Standard Cell Power Sharing
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Solution Overview
Problem
Aggressive channel-length scaling and wire-pitch scaling in semiconductor manufacturing face challenges such as increased electrical resistance and limited area savings, making it difficult to achieve effective area scaling in semiconductor devices.
Innovation Solution
The implementation of Zero Diffusion Break (ZDB) in a Place and Route (PNR) environment allows standard cells to share transistor source power connections, reducing design area and cost by eliminating dummy transistors and diffusion breaks at the cell boundaries, enabling power connections to overlap between adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If aggressive channel-length scaling is used for area scaling, then device area is reduced, but manufacturing suitability deteriorates
Solution Approach 1:
The patent merges power connections between adjacent standard cells by eliminating diffusion breaks at cell boundaries. This allows transistors in adjacent cells to share common diffusion regions, reducing the need for separate power connections and dummy transistors. The merging of previously isolated diffusion regions enables area reduction while maintaining manufacturability through shared power infrastructure.
Solution Approach 2:
The patent extracts and removes diffusion breaks from standard cell boundaries, eliminating the artificial separation between adjacent cells. By taking out these diffusion breaks, the design enables continuous diffusion regions across cell boundaries, allowing aggressive scaling without compromising the manufacturing process requirements for power connection isolation.
2Area of moving object
If wire-pitch scaling is used for area scaling, then device area is reduced, but electrical resistance increases
Solution Approach 1:
The patent merges power connection pathways between adjacent cells by eliminating diffusion breaks, creating longer continuous diffusion regions. This merging reduces the number of discrete connection points and associated contact resistance, compensating for the increased resistance from reduced wire pitch. The shared diffusion regions provide lower resistance power distribution paths.
3Ease of manufacture
If standard diffusion breaks are used at cell boundaries, then manufacturing is simplified, but area efficiency deteriorates
Solution Approach 1:
The patent extracts diffusion breaks from standard cell boundaries, removing the manufacturing-friendly but area-inefficient isolation structures. By taking out these diffusion breaks, the design achieves continuous diffusion regions that eliminate wasted space while maintaining power connection integrity through shared transistors and diffusion regions between adjacent cells.
Solution Approach 2:
The patent merges diffusion regions across cell boundaries, combining previously separate power connection structures into shared regions. This merging eliminates the need for separate diffusion breaks at each cell boundary, reducing total area while maintaining manufacturing feasibility through the shared power infrastructure that serves multiple cells.
4Reliability
If diffusion breaks are maintained for power connections, then power connection reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges power connection structures between adjacent cells by eliminating diffusion breaks, creating shared diffusion regions that serve multiple cells. This merging reduces device complexity by removing redundant power connection elements such as dummy transistors and isolated diffusion regions, while maintaining power connection reliability through the shared continuous diffusion paths.
Solution Approach 2:
The patent implements universal diffusion regions that serve multiple functions: they provide power connections for transistors in adjacent cells simultaneously. This multi-functionality reduces the need for dedicated power connection structures in each cell, simplifying the overall device design while maintaining reliable power distribution across cell boundaries.
Data Source
AI summary
A standard cell in a Place and Route (PNR) library of standard cells includes a cell boundary and cell configuration information. The cell boundary includes a first edge and a second edge that is opposite the first edge. The cell configuration information indicates a power connection configuration to be used with a second standard cell when the standard cell is placed next to the second standard cell in a layout in a PNR environment, such that at least one transistor source electrode is physically shared between the standard cell and the second standard cell. The cell configuration information may be edge identifier information for the first edge and/or the second edge of the first standard cell. The power connection configuration may also indicate that the power connection configuration for the first edge and/or the second edge is outside the cell boundary for the standard cell.