3D Standard Cell Layout With Zero Diffusion Break Isolation
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in efficiently designing and placing standard cells on a chip due to issues like capacitive coupling, electro migration, short channel effects, and inefficient use of space, which affect performance and yield, particularly with non-planar devices.
Innovation Solution
The use of vertically stacked non-planar transistors with zero diffusion breaks between standard cells, allowing for orthogonal orientation and reduced active layer dimensions, which enables efficient floor planning and reduces on-die area usage by eliminating unnecessary diffusion breaks and using a single via layer for connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If standard cells are placed with traditional diffusion breaks between them, then electrical isolation between cells is achieved, but on-die area increases and placement efficiency decreases
Solution Approach 1:
The patent removes the diffusion break structure entirely from between adjacent standard cells. By extracting this isolation element, the invention eliminates the area penalty while maintaining electrical isolation through alternative means (inverted well structures and substrate connections), thereby resolving the contradiction between area efficiency and electrical isolation.
Solution Approach 2:
The invention merges adjacent standard cells by eliminating diffusion breaks between them. Multiple cells are placed directly adjacent to each other without intervening isolation structures, creating a continuous active region that improves area utilization while maintaining proper electrical isolation through the inverted well architecture.
2Area of stationary object
If vertically stacked non-planar transistors are used, then on-die area is reduced and floor planning efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar transistor structures to vertically stacked three-dimensional transistors. By moving into the vertical dimension, the invention achieves higher device density and reduced on-die area footprint while maintaining compatibility with standard manufacturing processes through self-aligned fabrication techniques.
3Loss of time
If automated place-and-route tools are used, then design cycle time is reduced, but layout rules must be rewritten for non-planar devices
Solution Approach 1:
The invention creates a universal standard cell layout architecture using inverted well structures that can accommodate both planar and non-planar transistor devices. This multi-functional approach allows existing automated place-and-route tools to work with minimal rule modifications while supporting advanced three-dimensional transistor structures.
Data Source
AI summary
An apparatus and method for efficiently creating layout of standard cells to improve floor planning of a chip. In various implementations, an integrated circuit uses multiple standard cells with an absence of diffusion breaks at cell boundaries. The standard cells use vertically stacked non-planer transistors. Multiple transistors are formed with an active region having a length between a source region and a drain region of a single transistor. Therefore, the active regions of these transistors are not formed across multiple gate terminals. By having active regions of these transistors formed across a single gate terminal of a single transistor, there is sufficient spacing to provide electrical isolation between two active regions of the two adjoining standard cells. This is true even when the two adjoining standard cells share a source/drain region at the cell boundaries. Accordingly, forming diffusion breaks at the edges of these standard cells can be skipped.