Computational Memory Zero Disable With Matrix Error Checking

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Solution Overview

Problem

Deep learning neural networks require significant power consumption due to data movement between memory and processing elements, leading to inefficiencies such as increased complexity, processing time, and larger chip area requirements, particularly in battery-powered devices.

Innovation Solution

A processing device with an array of processing elements connected for direct communication, featuring an input zero detector and zero disable circuit to optimize data movement, and a controller that adds error-checking values to matrices for efficient parallel operations and error detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is moved between memory and processing elements in traditional computer architecture, then computations can be performed, but power consumption increases significantly

Engineering Contradiction:
Improvecomputational throughputVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The system segments the computational array into multiple independently controllable processing elements that can be selectively activated. Each processing element can be enabled or disabled based on whether its input data is non-zero, allowing fine-grained power management while maintaining computational throughput across the array.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically adjusts the operational state of processing elements based on input data characteristics. The enablement/disablement of processing elements is determined in real-time based on whether input values are zero or non-zero, creating a dynamic power management system that adapts to the computational workload.

Inventive Principle:
Principle #15Dynamics

2Use of energy by moving object

If processing elements are disabled to save power, then energy consumption decreases, but processing capability is reduced

Engineering Contradiction:
Improvepower consumptionVSAvoidcomputational throughput
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The system applies different operational states to different processing elements based on their specific input data. Rather than uniformly disabling entire blocks of processing elements, the system selectively disables only those individual elements receiving zero inputs, maintaining processing capability in regions with non-zero data while saving power in regions with zero data.

Inventive Principle:
Principle #3Local quality

3Reliability

If zero inputs are processed normally, then computational accuracy is maintained, but unnecessary power is consumed

Engineering Contradiction:
Improvecomputational accuracyVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system converts the potentially harmful effect of zero inputs (which waste power when processed) into a beneficial control signal. The zero detector identifies zero inputs and uses them to trigger the disablement of processing elements, thereby transforming what would be a power-wasting condition into a power-saving opportunity while maintaining computational accuracy through proper handling of zero values.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

4Reliability

If error checking is implemented in neural network computations, then computational reliability improves, but processing complexity increases

Engineering Contradiction:
Improvecomputational accuracyVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system performs preliminary error detection by monitoring input values for zero conditions before they enter the main computational path. By detecting zeros upfront and disabling affected processing elements, the system prevents erroneous computations from propagating through the array, providing a form of preliminary error checking that simplifies the overall error handling mechanism.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11342944B2Computational memory with zero disable and error detection
Publication Date: 2022.05.24 AT-MEMORY COMPUTING LP
  • US11342944B2 patent drawing
  • US11342944B2 patent drawing
  • US11342944B2 patent drawing

AI summary

A processing element includes an input zero detector to detect whether the input from the neighbor processing element contains a zero. When the input from the neighbor processing element contains the zero, a zero disable circuit controls the input from the neighbor processing element and respective data of the memory to both appear as unchanged to the arithmetic logic unit for the operation. A controller of an array of processing elements adds a row of error-checking values to a matrix of coefficients, each error-checking value of the row of error-checking values being a negative sum of a respective column of the matrix of coefficients. The controller controls a processing element to perform an operation with the matrix of coefficients and an input vector to accumulate a result vector. Owing to the error-checking values, when a sum of elements of the result vector is non-zero, an error is detected.