Zero Flag Bit Generation Circuit for Multiplier Speed
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Solution Overview
Problem
The longer operation time of existing multipliers in 32-bit architecture MCUs limits the MCU operation frequency due to their critical path length, necessitating a method to accelerate multiplier operations.
Innovation Solution
A generating circuit for the zero flag bit of a multiplier, comprising a low-bit zero detecting module, a bitwise-AND module, and a result determining module, which detects the first occurrence of a value 1 in the input values, reverses their order, performs a bitwise-AND operation, and determines whether the result is zero, allowing for parallel computation of the zero flag bit without needing the full multiplication result.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a traditional 32x32 multiplier is used to ensure accurate multiplication results, then the computation accuracy is improved, but the operation time increases and limits the MCU frequency
Solution Approach 1:
The patent applies preliminary action by computing the zero flag bit in parallel with the multiplication operation rather than waiting for the multiplication to complete. The zero flag detection circuit independently processes the input operands A and B to determine if the result will be zero, allowing this flag to be ready before the multiplication finishes, thus reducing the overall operation time without sacrificing accuracy
Solution Approach 2:
The patent segments the multiplier operation into independent parallel tasks: the main multiplication computation and the zero flag detection. By separating these functions into different computational paths, the system can proceed with both simultaneously, eliminating the sequential dependency that previously extended the critical path and operation time
2Productivity
If the critical path of the multiplier is reduced to improve operation speed, then the productivity is improved, but the complexity of the circuit increases
Solution Approach 1:
The zero flag detection circuit performs preliminary evaluation of the multiplication result before the actual multiplication completes. By checking if either operand is zero at the beginning and setting the zero flag accordingly, the circuit avoids waiting for the full multiplication to finish, thereby shortening the critical path and improving operation speed without requiring complex additional logic
Solution Approach 2:
The patent extracts the zero flag detection function from the main multiplication computation path. This separate extraction allows the zero flag to be determined independently through a simpler, faster circuit that operates in parallel, reducing the overall operation time without significantly increasing the complexity of the core multiplication unit
Data Source
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AI summary
The present invention relates to the technical field of integrated circuits and discloses a generating circuit for the zero flag bit of a multiplier. The generating circuit is used for application of the multiplier which requires the number of bits of the multiplication operation result to be the same as that of the multiplicator and that of the multiplicand and includes a low-bit zero detecting module, a bitwise-AND module, and a result determining module, where the low-bit zero detecting module is used for discovering the bit in which the value of 1 appears first in the first input value from low bit to high bit, and replacing all bits from the bit to the highest bit with 1; the bitwise-AND module is used for reversing the order of the first input value bit by bit after replacement, and then carrying out a bitwise-AND logical operation on the first input value after order reversing and a second input value; and the result determining module is used for determining whether all the results of the logical AND operation are zero, if yes, the zero flag bit outputs 1, otherwise it outputs 0. The circuit disclosed by the present invention is compact in structure, convenient to control, and convenient for being popularized and promoted.