Zero-Misalignment Via-Pad Structures for 2.5D Packaging
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Solution Overview
Problem
Conventional electronic device packaging methods face challenges with via-pad misalignment, leading to device failures, reduced yield, and increased manufacturing costs due to the large size of pads and limited via registration capability, which restricts the density of metal lines and components on the substrate.
Innovation Solution
The implementation of zero-misalignment via-pad structures using a dual-tone photoresist in additive and semi-additive metallization processes, allowing for precise alignment of via-pad structures by utilizing a rigid, planar photomask, thereby reducing pad sizes and increasing the density of metal lines and components on the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If large pads are used to accommodate misalignment, then via-to-pad registration is improved, but device density and manufacturing cost are worsened
Solution Approach 1:
The patent applies preliminary action by forming the pad structure before the via structure in a self-aligned process. The pad is deposited and patterned first, then used as a registration feature for subsequent via formation, eliminating the need for separate alignment steps and fiducial markers. This preliminary positioning ensures zero misalignment while maintaining small pad dimensions for high device density.
2Manufacturing precision
If large pads are used to accommodate misalignment, then via-to-pad registration is improved, but manufacturing cost is worsened
Solution Approach 1:
The self-aligned process performs the alignment function during the pad formation step itself, rather than requiring separate alignment operations. The pad structure is created with precise dimensions and positioning as part of the standard deposition and patterning sequence, eliminating costly alignment tools, fiducial markers, and manual registration steps.
3Ease of manufacture
If conventional laser drilling or etching is used for via formation, then via creation is simplified, but via-to-pad misalignment occurs due to dielectric shrinkage
Solution Approach 1:
The patent performs the critical alignment action preliminarily during pad formation rather than during via formation. The pad is patterned with precise dimensions and positioned exactly where needed, then serves as the alignment reference for subsequent via creation. This eliminates the misalignment problem caused by dielectric shrinkage during curing, as the alignment is already established before the dielectric is deposited and cured.
4Manufacturing precision
If fiducial markers are used for via registration, then alignment capability is improved, but device density is worsened due to space requirements
Solution Approach 1:
The patent extracts and eliminates the fiducial marker component from the alignment system. Instead of adding separate fiducial markers that occupy space on the substrate, the alignment function is integrated into the pad structure itself. The pad serves dual purposes: as an electrical connection element and as the alignment reference feature, removing the need for dedicated fiducial space and increasing available area for functional metal lines.
5Manufacturing precision
If standard packaging techniques with large pads are used, then via-to-pad registration is maintained, but scalability and z-height are worsened
Solution Approach 1:
The self-aligned process establishes precise via-to-pad registration preliminarily during pad formation, enabling subsequent packaging architectures that require high precision and low profile. This approach supports advanced packaging techniques such as 2.5D integration and chip-on-substrate configurations where small pad sizes and precise alignment are critical for achieving low z-height and high scalability without registration errors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly decreases via and pad sizes, enhances the density of input/output connections, reduces manufacturing costs, and improves electrical performance by enabling 2.5D packaging without the need for silicon interposers or bridges, leading to increased scalability and reduced z-height.
Implementation Method 1
A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure
Data Source
AI summary
A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.