Zero-Value Multiplication Detection Circuit for Power Reduction
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Solution Overview
Problem
Current processor architectures lack efficient mechanisms to optimize hardware performance and power consumption by skipping unnecessary multiplication operations involving zero values, which are common in neural networks and other computational systems.
Innovation Solution
Incorporating a 'zeros' mode in circuitry that includes a 'zeros' detector circuit coupled to a 'zeros' multiplier circuit, allowing the processor to identify and skip zero-value multiplications, thereby conserving power by turning off multiplier circuits when zero inputs are detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional multiplication circuitry is used without zero detection, then all multiplication operations are performed uniformly, but power is wasted on unnecessary multiplications involving zero values
Solution Approach 1:
The patent applies preliminary action by detecting zero values in input operands before the multiplication operation is executed. The zero detection circuit examines the input values and generates control signals in advance, allowing the system to skip unnecessary multiplication operations and reduce power consumption before the actual computational work would begin.
Solution Approach 2:
The patent implements dynamics by making the multiplication circuit's operation state variable and controllable. The circuit can dynamically switch between performing full multiplication operations and skipping operations based on real-time detection of zero values in the inputs. This dynamic adaptation allows the system to optimize power consumption based on the actual data being processed.
2Use of energy by moving object
If zero multiplication operations are skipped, then power consumption is reduced, but processing time may increase due to additional detection steps
Solution Approach 1:
The patent merges the zero detection function with the multiplication operation circuitry itself, rather than using separate sequential stages. The detection and multiplication operations are integrated at the circuit level, allowing both functions to occur in parallel or overlapping timeframes. This merging eliminates the need for separate detection and execution phases, preventing additional processing time while still achieving power savings.
3Loss of energy
If a zeros detector circuit is added to identify zero values, then unnecessary multiplications can be skipped, but the device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the multiplication operation into distinct functional components: a zero detection circuit that examines input values, a control logic unit that decides whether to perform multiplication, and the multiplication circuitry itself. This segmentation allows each component to be optimized independently and enables the system to skip the power-intensive multiplication stage when zero values are detected, achieving energy savings with minimal overall complexity increase.
4Productivity
If multiplication operations are performed on all input values without selection, then processing is simple and uniform, but power is wasted on operations that will always result in zero
Solution Approach 1:
The patent implements self-service by enabling the computational system to automatically identify and eliminate wasteful operations through built-in zero detection circuitry. The system serves itself by monitoring its own input data, detecting zero values, and autonomously deciding to skip unnecessary multiplication operations. This self-monitoring and self-optimization capability improves computational efficiency without requiring external control or manual intervention.
Data Source
AI summary
Systems, methods, and apparatuses relating to instructions to multiply values of zero are described. In one embodiment, a hardware processor includes a decoder to decode a single instruction into a decoded single instruction, the single instruction having a first field that identifies a first number, a second field that identifies a second number, and a third field that indicates a number format for the first number and the second number; and an execution circuit to execute the decoded single instruction to: cause a first comparison of the first number to a zero value in the number format of the first number, cause a second comparison of the second number to a zero value in the number format of the second number, provide as a resultant of the single instruction a value of zero when the second comparison indicates the second number equals the zero value in the number format of the second number, provide as the resultant of the single instruction the value of zero when the first comparison indicates the first number equals the zero value in the number format of the first number, and provide as the resultant of the single instruction a product of a multiplication of the first number and the second number when the first comparison indicates the first number does not equal the zero value in the number format of the first number and the second comparison indicates the second number does not equal the zero value in the number format of the second number.