Zero-Pin IC Testing via Embedded Test Controller Pin Reconfiguration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern integrated circuits face challenges in testing due to the limited number of pins available, making it difficult to implement design-for-testability (DFT) functionality without additional pins, which is crucial for efficient testing and debugging.
Innovation Solution
The integration of an embedded test controller within the IC that repurposes existing pins for testing by generating signals to change the input/output function of pins and apply test functions to data storage elements, allowing for full testing without the need for dedicated test pins, thereby enabling zero-pin DFT solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated test pins are added to the integrated circuit, then testing capability is improved, but pin count and device complexity increase
Solution Approach 1:
The patent applies multi-functionality by enabling existing I/O pins to serve dual purposes: normal operational functions during standard operation and test functions during testing mode. The test controller dynamically reconfigures pin functions, allowing the same physical pins to be used for both operational data I/O and test data input/output, thereby eliminating the need for separate dedicated test pins.
Solution Approach 2:
The patent implements dynamic reconfiguration of pin functions through a test controller that can change the operational mode of pins between normal operation and test mode. The controller dynamically assigns different functions to pins based on the operational state, enabling flexible switching between operational I/O and test I/O without requiring additional static test pins.
2Reliability
If scan chains are embedded into the integrated circuit for testing, then testability is enhanced, but the number of externally accessible scan chains increases pin requirements
Solution Approach 1:
The patent makes existing I/O pins universal by enabling them to function as scan chain input/output pins during testing mode while maintaining their normal operational functions. The test controller configures selected I/O pins to serve as scan chain interfaces, allowing the same pins to be used for both operational data communication and test pattern input/output without requiring separate dedicated scan pins.
Solution Approach 2:
The patent merges the functional roles of operational I/O pins and test I/O pins by allowing the same physical pins to handle both operational data and test data. The test controller combines the operational mode and test mode functionalities into a unified pin structure, eliminating the need for separate dedicated test pins and reducing overall pin count.
3Adaptability or versatility
If multiplexers are introduced to select between testing and non-testing modes, then mode switching capability is improved, but device complexity and pin count increase
Solution Approach 1:
The test controller is implemented as an embedded self-contained unit within the integrated circuit that autonomously manages mode switching between operational mode and test mode. The controller generates internal control signals to reconfigure pin functions and coordinate test operations without requiring external control logic or additional mode-select pins, thereby achieving mode switching capability while minimizing additional device complexity.
Data Source
AI summary
In some aspects, the present disclosure provides a method for testing an integrated circuit (IC). In some configurations, the method includes determining, by a test controller embedded in the IC, a change in operation of the IC from a normal mode to a test mode. The method also includes communicating, by the test controller to a chain of data storage elements in the IC: a first test signal configured to change an input/output (I/O) function of a first IC pin, and a second test signal configured to apply one of a plurality of test functions to each data storage element in the chain of data storage elements. The method also includes, receiving, via a second IC pin, a test clock signal configured to control a latch function of each data storage element in the chain of data storage elements.