Zero Threshold Voltage FinFET via Local N-Well Doping
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Solution Overview
Problem
Existing FinFET technologies face challenges in designing and fabricating zero threshold voltage (ZVt) devices due to unworkable processes that affect threshold voltage adjustment, particularly at the 14 nm form factor, leading to higher threshold voltages and limited dynamic range for analog signals.
Innovation Solution
Forming a first N+ region and a second N+ region on a finned substrate with a p-well construction, and doping the region between them with a negative implant species to create an n-well, allowing adjustment of the threshold voltage to achieve a zero threshold voltage FinFET device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional FinFET fabrication processes are used, then device scalability is achieved, but threshold voltage adjustment becomes unworkable and threshold voltage increases
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming N+ source/drain regions first, then creating the n-well in the region between them. This segmentation allows independent optimization of each step and enables precise threshold voltage control without disrupting the overall FinFET fabrication flow
Solution Approach 2:
The N+ source and drain regions are formed in advance before creating the n-well. This preliminary action establishes the boundaries for subsequent n-well formation and allows the threshold voltage adjustment to be integrated into the existing fabrication sequence without requiring additional masking steps
2Reliability
If higher threshold voltage is used, then device control is improved, but dynamic range for analog signals is limited
Solution Approach 1:
The threshold voltage parameter is changed from conventional positive values to zero threshold voltage through controlled n-well doping. This parameter change enables the device to operate with enhanced dynamic range while maintaining adequate control through the FinFET structure's inherent electrostatics
Solution Approach 2:
The n-well is formed locally in the region between the N+ source and drain regions, creating a localized doping profile that adjusts the threshold voltage specifically in the channel region without affecting other device characteristics. This local modification enables precise control over the threshold voltage parameter
3Manufacturing precision
If additional masks or processing steps are added, then threshold voltage adjustment precision is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The n-well formation process serves multiple functions: it defines the channel region, adjusts the threshold voltage, and establishes the doping profile. By combining these functions into a single processing step, the invention achieves precise threshold voltage control without adding masking or alignment complexity
Solution Approach 2:
The threshold voltage adjustment is merged with the existing FinFET fabrication process by utilizing the same doping and thermal processing steps. The n-well formation is integrated into the flow between source/drain formation and gate fabrication, eliminating the need for separate adjustment steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the production of zero threshold voltage FinFET devices without additional masks or processing steps, improving signal range and operational bandwidth by optimizing threshold voltage and performance parameters like capacitance and frequency.
Implementation Method 1
doping a region of the finned substrate located between the first N+ region and the second N+ region with a negative implant species forming an n-well
Data Source
AI summary
Approaches for altering the threshold voltage (e.g., to zero threshold voltage) in a fin-type field effect transistor (FinFET) device are provided. In embodiments of the invention, a first N+ region and a second N+ region are formed on a finned substrate that has a p-well construction. A region of the finned substrate located between the first N+ region and the second N+ region is doped with a negative implant species to form an n-well. The size and/or composition of this n-well region can be adjusted in view of the existing p-well construction of the substrate device to change the threshold voltage of the FinFET device (e.g., to yield a zero threshold voltage FinFET device).