Safety Test Circuit Using Zero-Vector PWM Windows

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Solution Overview

Problem

Safety tests for industrial machines' safety circuits, such as those in Variable-Frequency Drives (VFDs), disrupt normal operation due to pulse testing methods that interfere with Pulse-Width Modulated (PWM) control signals, especially when their frequencies are similar.

Innovation Solution

A safety test circuit with two independent safety channels that perform tests during zero-vector periods when all power control signals are inactive, ensuring no disruption to the power module's operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If pulse testing is performed during normal operation, then safety circuit reliability is improved, but machine operation efficiency deteriorates due to disruption of PWM control signals

Engineering Contradiction:
Improvesafety circuit reliabilityVSAvoidmachine operation efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by performing safety tests during pre-identified zero-vector periods when PWM control signals are naturally inactive. The control circuit is configured to detect zero-vector states and schedule pulse tests during these predetermined time windows, ensuring safety verification occurs before any potential interference with active control signals could occur.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements periodic action by utilizing the periodic zero-vector intervals inherent in PWM operation cycles. Safety tests are conducted at regular intervals during these zero-vector periods, synchronizing the testing rhythm with the existing PWM frequency to ensure both safety verification and minimal disruption to power module operation.

Inventive Principle:
Principle #19Periodic action

2Reliability

If pulse testing frequency is increased to improve safety verification, then safety reliability is improved, but interference with PWM control signals worsens

Engineering Contradiction:
Improvesafety verification frequencyVSAvoidsignal interference
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by spatially separating safety test operations from PWM control operations in the time domain. The control circuit identifies specific zero-vector time windows and confines pulse tests to these localized periods, ensuring that high-frequency safety testing occurs only in regions where no PWM control signals are active, thus eliminating signal interference.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements dynamics by making the pulse test timing adaptive to the real-time PWM operating conditions. The control circuit dynamically adjusts the timing of safety tests based on detected zero-vector periods, allowing the testing frequency to be maximized within the constraints of avoiding interference with active control signals.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12597764B2Safety test circuit and method
Publication Date: 2026.04.07 ROCKWELL AUTOMATION TECH INC
  • US12597764B2 patent drawing
  • US12597764B2 patent drawing
  • US12597764B2 patent drawing

AI summary

A safety test circuit includes a pulse test control circuit configured to receive a zero-vector signal and to generate a pulse test signal when the zero-vector signal is active, and first and second safety channels. The first safety channel includes a first enable circuit configured to receive the pulse test signal and a first safety input signal, and to generate a first enable signal which is active only when both the pulse test signal and the first safety input signal are inactive, and a first power signal gate configured to receive a first plurality of power control signals and to transfer the first plurality of power control signals to a power module only when the first enable signal is active. The second safety channel includes a second enable circuit configured similar to the first enable circuit, and a second power signal configured similar to the first power signal gate.