Zero-Voltage Switch-Mode Power Converter Timing Control
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Solution Overview
Problem
High-switching-frequency switch-mode power converters face inefficiencies due to transition conduction losses and thermal losses in power-FETs, as they require additional energy to actuate and experience higher resistance during switch transitions, leading to reduced power conversion efficiency.
Innovation Solution
The implementation of a switch-mode power converter with a bridge node, LC circuit, and pulse width modulation (PWM) and frequency control circuits, along with delay feedback circuits, to control switch transition times and minimize current through power-FETs during transitions, achieving zero-voltage switching by optimizing the timing of switch transitions using 'sample and hold' circuits and timing feedback control loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If switching frequency is increased to reduce component volume and cost, then power converter volume is reduced, but power conversion efficiency deteriorates due to additional energy required to actuate power-FETs and higher transition conduction losses
Solution Approach 1:
The patent applies preliminary action by pre-charging the bridge node capacitance to the input voltage level before closing the high-voltage switch. This is achieved through a dedicated pre-charge path that activates before the main switching event, ensuring the voltage across the power-FET is minimized at the moment of closure, thereby reducing transition conduction losses while maintaining high switching frequency operation
Solution Approach 2:
The patent introduces an intermediary pre-charge circuit consisting of a pre-charge switch and resistor network that mediates between the input voltage source and the bridge node capacitance. This intermediary circuit prepares the bridge node voltage in advance, allowing the main power-FET to switch with minimal voltage stress, thus reducing both transition losses and switching energy requirements
2Volume of moving object
If switching frequency is increased to reduce component volume and cost, then power converter volume is reduced, but transition conduction losses increase due to higher resistance during switch transitions
Solution Approach 1:
The patent applies preliminary action by pre-charging the bridge node capacitance to the input voltage level before closing the high-voltage switch. This is achieved through a dedicated pre-charge path that activates before the main switching event, ensuring the voltage across the power-FET is minimized at the moment of closure, thereby reducing transition conduction losses while maintaining high switching frequency operation
Solution Approach 2:
The patent converts the normally harmful transition period into a beneficial pre-conditioned state. By intentionally adding a pre-charge phase that lasts for a controlled duration, the system transforms what would be a lossy transition into a preparatory state where the power-FET switches with minimal voltage difference, effectively converting the transition period from a source of losses to a source of efficiency improvement
3Speed
If additional energy is expended to actuate power-FETs at high switching frequencies, then switching frequency can be increased, but power conversion efficiency deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-charging the bridge node capacitance to the input voltage level before closing the high-voltage switch. This is achieved through a dedicated pre-charge path that activates before the main switching event, ensuring the voltage across the power-FET is minimized at the moment of closure, thereby reducing transition conduction losses while maintaining high switching frequency operation
Solution Approach 2:
The patent changes the voltage parameter across the power-FET during switching transitions by introducing a pre-charge phase. The bridge node voltage is dynamically adjusted to match the input voltage before the main switch closes, effectively changing the voltage stress parameter from high to near-zero at the critical switching moment, thereby reducing the energy required to actuate the power-FET
Data Source
AI summary
A switched-mode power converter includes timing control feedback loop circuits to minimize or eliminate the potential difference across a high-power switch and a low-power switch during their transitions times. A first feedback circuit compares the measured voltage across the high-power switch at the moment the high-power switch closes with the input voltage to the high-power switch to control a low-to-high delay time. A second feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch closes with the input voltage to the low-power switch to control a high-to-low delay time. A third feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch opens. The output of the third feedback circuit is provided as inputs to the first and second feedback circuits. The third feedback circuit also controls the frequency of the power converter.