Zero-Forcing Receiver Equalization With Noise De-Whitening Mitigation
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Solution Overview
Problem
Conventional zero forcing equalizers in wireless communication systems are inefficient due to repetitive sequential computations, requiring significant chip real estate and increasing latency, and de-whiten noise elements, leading to degraded performance in downstream log-likelihood ratio computations and higher bit and packet error rates.
Innovation Solution
A receiver with a zero forcing equalizer that employs iterative and parallel computation algorithms, utilizing noise variance-based scaling factors to mitigate noise de-whitening, thereby reducing chip real estate requirements and latency, and improving accuracy in log-likelihood ratio-based signal decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional zero forcing equalizers use sequential computations to invert matrices, then computation accuracy is maintained, but latency increases and chip real estate requirements increase
Solution Approach 1:
The patent segments the matrix inversion computation into multiple parallel processing stages. Instead of performing sequential computations, the equalizer divides the matrix operations into independent parallel tasks that can be executed simultaneously across multiple processing units, thereby reducing latency while maintaining computational accuracy through structured parallel algorithms
Solution Approach 2:
The patent transitions from sequential one-dimensional computation to multi-dimensional parallel processing by utilizing multiple processing units operating simultaneously. This dimensional expansion allows matrix inversion to be performed across parallel dimensions rather than sequential steps, reducing overall computation time while preserving accuracy through coordinated multi-unit processing
2Measurement precision
If conventional zero forcing equalizers use sequential computations, then computation accuracy is maintained, but chip real estate requirements increase
Solution Approach 1:
The patent merges multiple computation functions into unified parallel processing units. By combining matrix inversion, equalization, and noise de-whitening operations into integrated parallel processing blocks, the design reduces the total chip area required compared to separate sequential processing units, while maintaining computational accuracy through coordinated processing
Solution Approach 2:
The patent creates universal processing units that can perform multiple functions including matrix operations, equalization, and noise processing simultaneously. These multi-functional units reduce chip real estate by eliminating the need for separate dedicated circuits for each function, while maintaining accuracy through unified processing architecture
3Productivity
If zero forcing equalization de-whitens noise elements, then equalization is performed, but LLR computation accuracy degrades and bit error rate increases
Solution Approach 1:
The patent applies preliminary counter-action by implementing noise de-whitening compensation before LLR computation. The system detects the de-whitening effect introduced by zero forcing equalization and applies compensating transformations to restore proper noise statistics, thereby preventing accuracy degradation in subsequent LLR computation and reducing bit error rates
Solution Approach 2:
The patent implements feedback mechanisms where the output of the equalizer is analyzed to detect noise de-whitening effects, and this information is fed back to adjust subsequent processing steps. The system uses feedback from noise statistics analysis to dynamically compensate for de-whitening, maintaining accurate LLR computation and reducing errors through continuous adjustment
Data Source
AI summary
This disclosure describes a receiver having equalization with noise de-whitening mitigation for wireless communication. An input port receives, via an antenna, a signal communicated over a wireless communication link, the signal comprising a noise component. Control circuitry performs zero forcing equalization of the received signal to generate a zero forcing equalization result signal. The zero forcing equalization causes de-whitening of the noise component by increasing a correlation among elements of the noise component. The control circuitry mitigates the de-whitening of the noise component by: determining a noise variance value based on channel properties of the wireless communication link, and modifying the zero forcing equalization result signal based on the noise variance value. The modified zero forcing equalization result signal is communicated, via an output port, to log-likelihood ratio (LLR) generation circuitry for LLR computation.