Zigzag Bit Line Structure for Flash Memory Capacitance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The reduction in pattern size of flash memory devices leads to increased crosstalk and capacitance between bit lines, which prolongs sensing time due to narrower distances between bit lines, necessitating an optimal balance between bit line thickness and distance to reduce capacitance and resistance.
Innovation Solution
A method of forming bit lines in a zigzag pattern with alternating metal layers and landing pads, where the second metal layers are buried only within trenches exposed by patterning the second interlayer insulating layer, allowing for increased pitch size and reduced capacitance between bit lines, thereby minimizing the distance between them and lowering resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch of metal lines is reduced to obtain higher device capacity, then device capacity increases, but the space between bit lines shrinks causing increased capacitance and crosstalk
Solution Approach 1:
The patent transitions from a conventional planar metal line arrangement to a three-dimensional stacked structure with alternating odd and even bit lines in different layers. This vertical stacking approach allows higher integration capacity while maintaining adequate horizontal spacing between lines in the same layer, thereby reducing capacitance and crosstalk through spatial separation in the vertical dimension.
Solution Approach 2:
The bit lines are segmented into odd-numbered and even-numbered lines that are physically separated into different layers. This segmentation allows each layer to have sufficient line spacing for reduced capacitance, while the overall structure achieves high density through vertical integration of multiple segmented line sets.
2Object-affected harmful factors
If the thickness of bit line is reduced to decrease capacitance, then capacitance decreases, but the resistance of bit line increases
Solution Approach 1:
The patent compensates for reduced line thickness by utilizing the vertical dimension through multi-layer stacking. While individual lines in each layer can be thinner to reduce capacitance, the overall conductive path benefits from the parallel arrangement of multiple layers, maintaining acceptable resistance while achieving lower capacitance through reduced lateral dimensions.
3Productivity
If the distance between bit lines is reduced to increase integration, then integration increases, but the capacitance between bit lines increases prolonging sensing time
Solution Approach 1:
The patent achieves high integration density by stacking bit lines in multiple vertical layers with alternating odd and even numbering. This vertical arrangement allows the horizontal distance between lines in the same layer to be maintained at sufficient levels for low capacitance, while the overall integration is increased through the addition of multiple layers in the vertical dimension, thereby reducing sensing time.
Data Source
AI summary
A method for forming a semiconductor device includes forming drain contact holes in a first interlayer insulating layer provided over a semiconductor substrate. First metal material is formed over the first interlayer insulating layer and fills the drain contact holes. A first metal layer formed by patterning the first metal material includes first lines and landing pads. Trenches formed in a second interlayer insulating layer formed over the patterned first metal material expose the landing pads. A second metal layer is formed by providing second metal material over the second interlayer insulating layer and filling the trenches. The second metal layer includes second lines within the trenches that contact the landing pads. The first and second metal layers define a first metal level of the semiconductor device. The first lines define odd-number lines of the first metal level, and the second lines define even-number lines of the first metal level.