Integrated Circuit Device With Zigzag Gate Electrodes
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Solution Overview
Problem
Current memory devices face challenges in efficiently selecting and switching memory cells due to limitations in interconnect selection mechanisms, leading to instability and reduced integration density.
Innovation Solution
The integrated circuit device employs a semiconductor substrate with strategically arranged semiconductor members and gate electrodes in a zigzag configuration, allowing for precise selection and switching of memory cells by controlling the potential applied to gate electrodes, thereby ensuring high ON/OFF current ratios and stable operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional interconnect selection mechanisms are used to select memory cells, then memory cell selection can be performed, but half-selected members are incorrectly switched to ON state leading to instability and reduced integration density
Solution Approach 1:
The gate electrode is divided into multiple independent gate electrodes (first gate electrode and second gate electrode) that can be controlled separately. Each gate electrode controls a specific portion of the semiconductor member, allowing precise selection of memory cells while preventing half-selected members from switching to ON state. This segmentation enables reliable interconnect selection without requiring complex selection mechanisms.
2Quantity of substance
If memory cells are integrated two-dimensionally or three-dimensionally to increase integration density, then more memory cells can be packed, but selection and switching becomes less efficient
Solution Approach 1:
The patent implements a three-dimensional memory structure where semiconductor members extend in the vertical direction (third direction) perpendicular to the substrate surface. Multiple gate electrodes are positioned at different heights and locations to control different portions of the semiconductor members. This spatial arrangement in three dimensions enables high integration density while maintaining efficient selection through vertical stacking and multi-level gate control.
3Adaptability or versatility
If multiple interconnects are provided parallel to each other for memory cell selection, then more memory cells can be addressed, but the selection mechanism becomes less efficient and more unstable
Solution Approach 1:
Different gate electrodes are positioned to control different local regions of the semiconductor members. The first gate electrode controls a first portion while the second gate electrode controls a second portion. By applying voltages selectively to specific gate electrodes, the patent achieves precise local control of current flow through semiconductor members, enabling stable and efficient selection of specific memory cells among multiple parallel interconnects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high integration density and stable operations by preventing half-selected members from being switched to the ON state, resulting in a significant improvement in the ratio of ON current to OFF current and maintaining device stability.
Implementation Method 1
The selection of the interconnect can be performed by connecting a TFT (Thin Film Transistor) to the interconnect and by switching the TFT ON/OFF
Data Source
AI summary
An integrated circuit device according to an embodiment includes a semiconductor substrate, a first semiconductor member and a second semiconductor member provided on the semiconductor substrate, a first electrode disposed between the first semiconductor member and the second semiconductor member, and a second electrode disposed between the semiconductor substrate and the first electrode. The first semiconductor member and the second semiconductor member extend in a first direction perpendicular to an upper surface of the semiconductor substrate. The first semiconductor member and the second semiconductor member are separated in a second direction orthogonal to the first direction. The first electrode extends in a third direction intersecting both the first direction and the second direction. The second electrode extends in the third direction.