Multilayer Chip Capacitor Zigzag Lead Arrangement
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Solution Overview
Problem
Multilayer chip capacitors face challenges in maintaining suitable Equivalent Series Resistance (ESR) while reducing Equivalent Series Inductance (ESL), leading to instability in power circuits due to excessive reduction of ESR and increased ESL.
Innovation Solution
The design incorporates a multilayer chip capacitor with internal electrode layers having one or two leads extending to the outer surface, arranged in a zigzag pattern, and external electrodes connected via these leads, ensuring horizontally adjacent leads of opposite polarities to cancel magnetic flux and maintain suitable ESR levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple leads are used in internal electrodes to reduce resistance, then ESR is reduced, but ESR becomes too small causing power circuit instability
Solution Approach 1:
The internal electrodes are divided into multiple blocks stacked in the stacking direction, with each block containing internal electrodes of a single polarity. This segmentation prevents excessive parallel connection of leads while maintaining reasonable resistance levels.
Solution Approach 2:
The patent introduces a stacking direction dimension by arranging internal electrode blocks vertically. Leads of vertically adjacent blocks are positioned horizontally adjacent to each other, creating a three-dimensional lead arrangement that reduces magnetic flux without excessive parallel connection.
2Loss of energy
If leads are arranged in interdigitated pattern to reduce ESL, then magnetic flux is canceled, but ESR becomes too small
Solution Approach 1:
Internal electrodes are segmented into multiple blocks stacked in the stacking direction. Each block contains internal electrodes of the same polarity, limiting the number of leads connected in parallel and preventing ESR from becoming too small.
Solution Approach 2:
The lead arrangement varies by location: leads of vertically adjacent blocks are horizontally adjacent to cancel magnetic flux (reducing ESL), while leads within the same block are not excessively parallel (maintaining ESR). This local differentiation resolves the contradiction.
3Volume of stationary object
If internal electrodes are arranged in vertical stacking to reduce capacitor size, then volume is reduced, but ESL increases due to current flowing in same direction
Solution Approach 1:
The capacitor is divided into multiple blocks stacked in the stacking direction, with each block containing internal electrodes of a single polarity. This segmentation enables vertical stacking for miniaturization while controlling lead arrangement to reduce ESL.
Solution Approach 2:
The patent transitions from two-dimensional planar arrangement to three-dimensional stacked arrangement. By positioning leads of vertically adjacent blocks horizontally adjacent to each other, magnetic flux cancellation is achieved in the vertical stacking configuration, reducing ESL despite compact volume.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces ESL, stabilizes power circuits, and prevents excessive reduction of ESR, thereby enhancing the overall stability and impedance matching of the power circuit.
Implementation Method 1
Since the leads adjacent to each other are supplied with voltages of opposite polarities, magnetic fluxes generated by high frequency currents applied from the external electrodes are canceled with each other between the adjacent leads and thus the ESL is reduced.
Implementation Method 2
The leads extending to the face of the capacitor body are arranged in a zigzag shape along the stacking direction.
Data Source
AI summary
A multilayer chip capacitor includes a capacitor body having dielectric layers, and internal electrode layers separated from each other in the capacitor body by the dielectric layers. Each internal electrode layer has one or two leads and includes at least one coplanar electrode plate. External electrodes are electrically connected to the internal electrode layers via the leads. The internal electrode layers constitute a plurality of blocks stacked repeatedly. Each block includes a plurality of the internal electrode layers stacked successively. The leads extending to a face of the capacitor body are arranged in a zigzag shape along a stacking direction. The leads of vertically adjacent ones of the electrode plates having opposite polarities are arranged to be horizontally adjacent to each other.