Zigzag PCB Wiring for Memory Signal Routing
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Solution Overview
Problem
The complexity of signal routing in high-speed memory modules makes it difficult to control the operating speed of memory devices, particularly in miniaturized electronic products with high capacity, high integration, and high performance requirements.
Innovation Solution
A zigzag wired memory module design is implemented, where the printed circuit board (PCB) has a multi-layer structure with alternating straight-line wirings connecting memory chips in a zigzag pattern, reducing signal path length and increasing space efficiency, thereby enhancing signal characteristics and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a fly-by type connection with daisy-chain topology is used to achieve high-speed operation, then signal transmission speed is improved, but routing complexity increases making it difficult to control operating speed
Solution Approach 1:
The patent applies asymmetry by arranging memory chips in a non-symmetric zigzag pattern rather than a conventional linear or symmetric grid layout. This asymmetric arrangement optimizes signal path lengths and reduces routing complexity while maintaining high-speed transmission capabilities. The zigzag configuration creates unequal spacing and positioning that simplifies the overall routing topology compared to traditional symmetric arrangements.
Solution Approach 2:
The patent transitions from a one-dimensional linear arrangement to a two-dimensional zigzag pattern on the PCB. By utilizing the additional spatial dimension, the signal paths can be optimized to reduce length and complexity while connecting multiple memory chips. This dimensional change allows for more efficient routing that avoids the complexity of purely linear daisy-chain connections.
2Quantity of substance
If numerous signals are routed through the PCB to connect multiple memory chips, then high capacity and high integration are achieved, but signal path length increases affecting operating speed control
Solution Approach 1:
The patent applies local quality by optimizing signal paths locally at each memory chip connection point. The zigzag arrangement ensures that each segment of the signal path is minimized locally, and the overall cumulative path length is reduced. This local optimization at each connection point collectively reduces the total signal path length across all memory chips while maintaining high signal density.
Solution Approach 2:
The zigzag pattern introduces curvature and non-linear paths that are more efficient than straight-line extensions. By using angled connections rather than extended linear paths, the signal routes bend in a zigzag manner that reduces overall path length while accommodating multiple chips. This curved/angular routing approach minimizes signal path length compared to conventional linear extensions.
Data Source
AI summary
A memory module includes a printed circuit board (PCB) including a multi-layer having a wiring structure formed therein. A length of the PCB in a first direction is longer than a length of the PCB in a second direction perpendicular to the first direction. A plurality of memory chips includes a plurality of solder balls. The plurality of memory chips is arranged in a first row and a second row respectively extending in the first direction on the PCB. The plurality of solder balls is continuously arranged in the first direction. The wiring structure alternately zigzag-connects the plurality of memory chips arranged in the first row and the second row.